Skip to content

Commit cc81a0b

Browse files
authored
Do not needlessly disable CPU features. (#59080)
On QEMU's RISC-V cpu, LLVM's `getHostCPUFeatures` reports: ``` +zksed,+zkne,+zksh,+zfh,+zfhmin,+zacas,+v,+f,+c,+zvknha,+a,+zfa,+ztso,+zicond,+zihintntl,+zvbb,+zvksh,+zvkg,+zbkb,+zvkned,+zvbc,+zbb,+zvfhmin,+zbkc,+d,+i,+zknh,+zicboz,+zbs,+zvksed,+zbc,+zba,+zvknhb,+zknd,+zvkt,+zbkx,+zkt,+zvfh,+zvkb,+m ``` We change that to: ``` +zksed,+zkne,+zksh,+zfh,+zfhmin,+zacas,+v,+f,+c,+zvknha,+a,+zfa,+ztso,+zicond,+zihintntl,+zvbb,+zvksh,+zvkg,+zbkb,+zvkned,+zvbc,+zbb,+zvfhmin,+zbkc,+d,+i,+zknh,+zicboz,+zbs,+zvksed,+zbc,+zba,+zvknhb,+zknd,+zvkt,+zbkx,+zkt,+zvfh,+zvkb,+m,-zcmop,-zca,-zcd,-zcb,-zve64d,-zve64x,-zve64f,-zawrs,-zve32x,-zimop,-zihintpause,-zcf,-zve32f ``` i.e. we add `-zcmop,-zca,-zcd,-zcb,-zve64d,-zve64x,-zve64f,-zawrs,-zve32x,-zimop,-zihintpause,-zcf,-zve32f`, disabling stuff `zve*` after first enabling `v` (which includes `zvl*b`). That's not valid: ``` LLVM ERROR: 'zvl*b' requires 'v' or 'zve*' extension to also be specified ``` ... so disable this post-processing of LLVM feature sets and trust what it spits out. AFAICT this only matters for the fallback path of `processor.cpp`, so shouldn't impact most users.
1 parent a39797a commit cc81a0b

File tree

1 file changed

+0
-13
lines changed

1 file changed

+0
-13
lines changed

src/processor.cpp

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -992,19 +992,6 @@ static std::string jl_get_cpu_features_llvm(void)
992992
attr.append(ele.getKey().str());
993993
}
994994
}
995-
// Explicitly disabled features need to be added at the end so that
996-
// they are not re-enabled by other features that implies them by default.
997-
for (auto &ele: HostFeatures) {
998-
if (!ele.getValue()) {
999-
if (!attr.empty()) {
1000-
attr.append(",-");
1001-
}
1002-
else {
1003-
attr.append("-");
1004-
}
1005-
attr.append(ele.getKey().str());
1006-
}
1007-
}
1008995
return attr;
1009996
}
1010997

0 commit comments

Comments
 (0)