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JulianKemmererJulianKemmerer
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First version of multi cycle riscv seems working
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‎examples/risc-v/mem_decl.h‎

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@@ -51,7 +51,9 @@ begin \n\
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#ifdef RISCV_IMEM_1_CYCLE
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// One cycle reads version
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#define riscv_imem_ram PPCAT(riscv_name,_imem_ram_one_cycle)
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#ifndef RISCV_IMEM_NO_AUTOPIPELINE
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PRAGMA_MESSAGE(FUNC_LATENCY riscv_imem_ram 1)
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#endif
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riscv_imem_ram_out_t riscv_imem_ram(
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uint32_t addr1,
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uint1_t valid1
@@ -154,7 +156,9 @@ begin \n\
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#ifdef RISCV_DMEM_1_CYCLE
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// One cycle reads version
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#define riscv_dmem_ram PPCAT(riscv_name,_dmem_ram_one_cycle)
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#ifndef RISCV_DMEM_NO_AUTOPIPELINE
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PRAGMA_MESSAGE(FUNC_LATENCY riscv_dmem_ram 1)
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#endif
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riscv_dmem_ram_out_t riscv_dmem_ram(
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uint32_t addr0,
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uint32_t wr_data0, uint1_t wr_byte_ens0[4],

‎examples/risc-v/multi_cycle_risc-v.c‎

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#pragma PART "xc7a35ticsg324-1l"
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#include "uintN_t.h"
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#include "intN_t.h"
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// RISC-V components
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#include "risc-v.h"
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// Include test gcc compiled program
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#include "gcc_test/text_mem_init.h"
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#include "gcc_test/data_mem_init.h"
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// Declare memory map information
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// Starts with shared with software memory map info
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#include "gcc_test/mem_map.h"
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// Define inputs and outputs
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typedef struct my_mmio_in_t{
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uint1_t button;
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}my_mmio_in_t;
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typedef struct my_mmio_out_t{
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uint32_t return_value;
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uint1_t halt;
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uint1_t led;
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}my_mmio_out_t;
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// Define the hardware memory for those IO
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RISCV_DECL_MEM_MAP_MOD_OUT_T(my_mmio_out_t)
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riscv_mem_map_mod_out_t(my_mmio_out_t) my_mem_map_module(
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RISCV_MEM_MAP_MOD_INPUTS(my_mmio_in_t)
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){
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// Outputs
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static riscv_mem_map_mod_out_t(my_mmio_out_t) o;
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o.addr_is_mapped = 0; // since o is static regs
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// Memory muxing/select logic
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// Uses helper comparing word address and driving a variable
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WORD_MM_ENTRY(o, THREAD_ID_RETURN_OUTPUT_ADDR, o.outputs.return_value)
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o.outputs.halt = wr_byte_ens[0] & (addr==THREAD_ID_RETURN_OUTPUT_ADDR);
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WORD_MM_ENTRY(o, LED_ADDR, o.outputs.led)
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return o;
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}
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// Declare a RISCV core type using memory info
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#define riscv_name my_riscv
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#define RISCV_IMEM_INIT text_MEM_INIT // from gcc_test/
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#define RISCV_IMEM_SIZE_BYTES IMEM_SIZE // from gcc_test/
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#define RISCV_DMEM_INIT data_MEM_INIT // from gcc_test/
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#define RISCV_DMEM_SIZE_BYTES DMEM_SIZE // from gcc_test/
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#define riscv_mem_map my_mem_map_module
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#define riscv_mem_map_inputs_t my_mmio_in_t
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#define riscv_mem_map_outputs_t my_mmio_out_t
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#include "multi_cycle_risc-v_decl.h"
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// Set clock of instances of CPU
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#define CPU_CLK_MHZ 60.0
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MAIN_MHZ(my_top, CPU_CLK_MHZ)
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// LEDs for demo
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#include "leds/leds_port.c"
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// Debug output ports for sim and hardware
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#include "debug_port.h"
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DEBUG_OUTPUT_DECL(uint1_t, unknown_op) // Unknown instruction
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DEBUG_OUTPUT_DECL(uint1_t, mem_out_of_range) // Exception, stop sim
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DEBUG_OUTPUT_DECL(uint1_t, halt) // Stop/done signal
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DEBUG_OUTPUT_DECL(int32_t, main_return) // Output from main()
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void my_top()
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{
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// Instance of core
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my_mmio_in_t in; // Disconnected for now
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my_riscv_out_t out = my_riscv(in);
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// Sim debug
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unknown_op = out.unknown_op;
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mem_out_of_range = out.mem_out_of_range;
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halt = out.mem_map_outputs.halt;
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main_return = out.mem_map_outputs.return_value;
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// Output LEDs for hardware debug
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leds = 0;
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leds |= (uint4_t)out.mem_map_outputs.led << 0;
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leds |= (uint4_t)mem_out_of_range << 1;
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leds |= (uint4_t)unknown_op << 2;
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}

‎examples/risc-v/multi_cycle_risc-v_decl.h‎

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// TODO rename defined things to be MULTI_CYCLE_RISCV_... etc
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#include "uintN_t.h"
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#include "intN_t.h"
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// Support old single core using mem_map_out_t
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#include "mem_map.h"
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#ifdef riscv_mem_map_outputs_t
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#define riscv_mmio_mod_out_t riscv_mem_map_mod_out_t(riscv_mem_map_outputs_t)
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#else
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#define riscv_mmio_mod_out_t mem_map_out_t
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#endif
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// Declare instruction and data memory
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// also includes memory mapped IO
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#define RISCV_IMEM_1_CYCLE
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#define RISCV_DMEM_1_CYCLE
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// Multi cycle is not a pipeline
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#define RISCV_IMEM_NO_AUTOPIPELINE
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#define RISCV_DMEM_NO_AUTOPIPELINE
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#define N_CYCLES 3
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#include "mem_decl.h"
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// CPU top level
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#define riscv_out_t PPCAT(riscv_name,_out_t)
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typedef struct riscv_out_t{
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// Debug IO
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uint1_t halt;
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uint32_t return_value;
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uint32_t pc;
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uint1_t unknown_op;
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uint1_t mem_out_of_range;
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#ifdef riscv_mem_map_outputs_t
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riscv_mem_map_outputs_t mem_map_outputs;
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#endif
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}riscv_out_t;
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riscv_out_t riscv_name(
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// Optional inputs to memory map
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#ifdef riscv_mem_map_inputs_t
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riscv_mem_map_inputs_t mem_map_inputs
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#endif
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)
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{
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// Top level outputs
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riscv_out_t o;
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// Instead of a counter for which stage is active
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// one hot bit is easier to work with (especially come time for pipelining)
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static uint1_t stage_valid[N_CYCLES] = {[0]=1}; // Starts in stage_valid[0]
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uint1_t next_stage_valid[N_CYCLES]; // Update static reg at end of func
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51+
// CPU registers (outside of reg file)
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static uint32_t pc = 0;
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o.pc = pc; // debug
54+
// Wires/non-static local variables from original single cycle design
55+
// are likely to be shared/stored from cycle to cycle now
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// so just declare all (non-FEEDBACK) local variables static registers too
57+
static uint32_t pc_plus4;
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static riscv_imem_ram_out_t imem_out;
59+
static decoded_t decoded;
60+
static reg_file_out_t reg_file_out;
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static execute_t exe;
62+
static uint1_t mem_wr_byte_ens[4];
63+
static uint1_t mem_rd_byte_ens[4];
64+
static uint32_t mem_addr;
65+
static uint32_t mem_wr_data;
66+
static riscv_dmem_out_t dmem_out;
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68+
// Cycle 0: PC
69+
if(stage_valid[0]){
70+
printf("PC in Cycle/Stage 0\n");
71+
// Program counter is input to IMEM
72+
pc_plus4 = pc + 4;
73+
printf("PC = 0x%X\n", pc);
74+
// Next state/cycle (potentially redundant)
75+
next_stage_valid = stage_valid;
76+
ARRAY_1ROT_UP(uint1_t, next_stage_valid, N_CYCLES)
77+
}
78+
79+
// Boundary shared between cycle0 and cycle1
80+
if(stage_valid[0]|stage_valid[1]){
81+
// Instruction memory
82+
imem_out = riscv_imem_ram(pc>>2, 1);
83+
}
84+
85+
// Cycle1: Decode
86+
if(stage_valid[1]){
87+
printf("Decode in Cycle/Stage 1\n");
88+
// Decode the instruction to control signals
89+
printf("Instruction: 0x%X\n", imem_out.rd_data1);
90+
decoded = decode(imem_out.rd_data1);
91+
if(decoded.print_rs1_read){
92+
printf("Read RegFile[%d] = %d\n", decoded.src1, reg_file_out.rd_data1);
93+
}
94+
if(decoded.print_rs2_read){
95+
printf("Read RegFile[%d] = %d\n", decoded.src2, reg_file_out.rd_data2);
96+
}
97+
o.unknown_op = decoded.unknown_op; // debug
98+
// Next state/cycle (potentially redundant)
99+
next_stage_valid = stage_valid;
100+
ARRAY_1ROT_UP(uint1_t, next_stage_valid, N_CYCLES)
101+
}
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103+
// Cycle1+2: Register file reads and writes
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// Reads are done during cycle1
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// Write back is next clock, cycle2
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// Register file write signals are not driven until later in code
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// but are used now, requiring FEEDBACK pragma
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uint5_t reg_wr_addr;
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uint32_t reg_wr_data;
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uint1_t reg_wr_en;
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#pragma FEEDBACK reg_wr_addr
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#pragma FEEDBACK reg_wr_data
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#pragma FEEDBACK reg_wr_en
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if(stage_valid[1]|stage_valid[2]){
115+
reg_file_out = reg_file(
116+
decoded.src1, // First read port address
117+
decoded.src2, // Second read port address
118+
reg_wr_addr, // Write port address
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reg_wr_data, // Write port data
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reg_wr_en // Write enable
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);
122+
// Next state/cycle (potentially redundant)
123+
next_stage_valid = stage_valid;
124+
ARRAY_1ROT_UP(uint1_t, next_stage_valid, N_CYCLES)
125+
}
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127+
// Cycle1: Execute
128+
if(stage_valid[1]){
129+
printf("Execute in Cycle/Stage 1\n");
130+
exe = execute(
131+
pc, pc_plus4,
132+
decoded,
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reg_file_out.rd_data1, reg_file_out.rd_data2
134+
);
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// Next state/cycle (potentially redundant)
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next_stage_valid = stage_valid;
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ARRAY_1ROT_UP(uint1_t, next_stage_valid, N_CYCLES)
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}
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// Boundary shared between cycle1 and cycle2
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// Data Memory inputs in stage1
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// Default no writes or reads
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ARRAY_SET(mem_wr_byte_ens, 0, 4)
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ARRAY_SET(mem_rd_byte_ens, 0, 4)
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uint32_t mem_addr = exe.result; // addr always from execute module, not always used
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uint32_t mem_wr_data = reg_file_out.rd_data2;
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if(stage_valid[1]){
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// Only write or read en during first cycle of two cycle read
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mem_wr_byte_ens = decoded.mem_wr_byte_ens;
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mem_rd_byte_ens = decoded.mem_rd_byte_ens;
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if(decoded.mem_wr_byte_ens[0]){
152+
printf("Write Mem[0x%X] = %d\n", mem_addr, mem_wr_data);
153+
}
154+
}
155+
// DMEM always "in use" regardless of stage
156+
// since memory map IO need to be connected always
157+
dmem_out = riscv_dmem(
158+
mem_addr, // Main memory read/write address
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mem_wr_data, // Main memory write data
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mem_wr_byte_ens, // Main memory write data byte enables
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mem_rd_byte_ens // Main memory read enable
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// Optional memory map inputs
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#ifdef riscv_mem_map_inputs_t
164+
, mem_map_inputs
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#endif
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);
167+
o.mem_out_of_range = dmem_out.mem_out_of_range; // debug
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// Optional outputs from memory map
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#ifdef riscv_mem_map_outputs_t
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o.mem_map_outputs = dmem_out.mem_map_outputs;
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#endif
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// Data memory outputs in stage2
173+
if(stage_valid[2]){
174+
// Read output available from dmem_out in second cycle of two cycle read
175+
if(decoded.mem_rd_byte_ens[0]){
176+
printf("Read Mem[0x%X] = %d\n", mem_addr, dmem_out.rd_data);
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}
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}
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// Cycle 2: Write Back + Next PC
181+
// default values needed for feedback signals
182+
reg_wr_en = 0; // default no writes
183+
reg_wr_addr = 0;
184+
reg_wr_data = 0;
185+
if(stage_valid[2]){
186+
printf("Write Back + Next PC in Cycle/Stage 2\n");
187+
// Reg file write back, drive inputs (FEEDBACK)
188+
reg_wr_en = decoded.reg_wr;
189+
reg_wr_addr = decoded.dest;
190+
// Determine reg data to write back (sign extend etc)
191+
reg_wr_data = select_reg_wr_data(
192+
decoded,
193+
exe,
194+
dmem_out.rd_data,
195+
pc_plus4
196+
);
197+
// Branch/Increment PC
198+
pc = select_next_pc(decoded, exe, pc_plus4);
199+
// Next state/cycle (potentially redundant)
200+
next_stage_valid = stage_valid;
201+
ARRAY_1ROT_UP(uint1_t, next_stage_valid, N_CYCLES)
202+
}
203+
204+
// Reg update
205+
stage_valid = next_stage_valid;
206+
207+
return o;
208+
}
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211+
#undef riscv_name
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#undef RISCV_IMEM_SIZE_BYTES
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#undef RISCV_DMEM_SIZE_BYTES
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#undef RISCV_IMEM_NUM_WORDS
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#undef RISCV_DMEM_NUM_WORDS
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#undef RISCV_IMEM_INIT
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#undef RISCV_DMEM_INIT
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#undef riscv_mem_map
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#undef riscv_mmio_mod_out_t
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#undef riscv_mem_map_inputs_t
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#undef riscv_mem_map_outputs_t
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#undef riscv_imem_ram_out_t
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#undef riscv_dmem_ram_out_t
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#undef riscv_imem_ram
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#undef riscv_dmem_ram
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#undef riscv_imem_out_t
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#undef riscv_dmem_out_t
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#undef riscv_imem
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#undef riscv_dmem
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#undef RISCV_IMEM_NO_AUTOPIPELINE
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#undef RISCV_DMEM_NO_AUTOPIPELINE

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