Merge branch 'master' into submodule_pycparser

Author: JulianKemmerer

README.md

@@ -0,0 +1,98 @@
+#include "intN_t.h"
+#include "uintN_t.h"
+
+#define N_THREADS 10
+
+// Each thread is providing these values to the increment handler module simultaneously
+uint32_t increment_input_value;
+uint32_t increment_input_tid;
+// And expects an output of the sum after the thread's addition (same cycle)
+uint32_t increment_output_sum;
+// A 'thread'/FSM instance definition trying to increment some accumulator this clock cycle
+uint32_t incrementer_thread(uint8_t tid)
+{
+  while(1)
+  {
+    increment_input_value = tid + 1;
+    increment_input_tid = tid;
+    // increment_output_sum ready same cycle
+    printf("Thread %d trying to increment by %d, got new total %d.\n",
+            tid, increment_input_value, increment_output_sum);
+    __out(increment_output_sum); // "return" that continues
+    //return increment_output_sum;
+  }
+}
+// Derive FSM from above function
+#include "incrementer_thread_FSM.h"
+
+// The module doing the incrementing/accumulating
+// sees an array of values, one from each thread
+uint32_t increment_input_values[N_THREADS];
+uint32_t increment_input_tids[N_THREADS];
+#pragma INST_ARRAY increment_input_value increment_input_values
+#pragma INST_ARRAY increment_input_tid increment_input_tids
+// And drives output totals back to each thread as an array
+uint32_t increment_output_sums[N_THREADS];
+#pragma INST_ARRAY increment_output_sum increment_output_sums
+#pragma MAIN increment_handler
+void increment_handler()
+{
+  // Accumulator reg
+  static uint32_t total;
+
+  // In one cycle accumulate from each thread with chained adders
+  uint32_t i;
+  for(i=0; i<N_THREADS; i+=1)
+  {
+    increment_output_sums[i] = total + increment_input_values[i];
+    printf("Thread %d incrementing total %d by %d -> new total %d.\n",
+            increment_input_tids[i], total, increment_input_values[i], increment_output_sums[i]);
+    total = increment_output_sums[i]; // accumulate
+  }
+
+  return total;
+}
+
+// Top level wrapper for N parallel instances of incrementer_thread
+
+// Connect FSM outputs to top level output
+// So doesnt synthesize away
+typedef struct n_thread_outputs_t
+{
+  incrementer_thread_OUTPUT_t data[N_THREADS];
+}n_thread_outputs_t;
+#pragma MAIN main
+n_thread_outputs_t main()
+{
+  // Registers keeping time count and knowning when done
+  static uint32_t clk_cycle_count;
+  printf("Clock Cycle %d:\n", clk_cycle_count);
+  
+  // N parallel instances of incrementer_thread
+  uint8_t tid;
+  incrementer_thread_INPUT_t inputs[N_THREADS];
+  n_thread_outputs_t outputs;
+  for(tid=0; tid<N_THREADS; tid+=1)
+  {
+    inputs[tid].tid = tid;
+    inputs[tid].input_valid = 1;
+    inputs[tid].output_ready = 1;
+    outputs.data[tid] = incrementer_thread_FSM(inputs[tid]);
+    //if(outputs.data[tid].input_ready)
+    //{
+    //  printf("Clock# %d: Thread %d starting.\n",
+    //    clk_cycle_count, tid);  
+    //}
+    //if(outputs.data[tid].output_valid)
+    //{
+    //  printf("Clock# %d: Thread %d output value = %d.\n",
+    //    clk_cycle_count, tid, outputs.data[tid].return_output);
+    //}
+  }
+  
+  // Func occuring each clk cycle
+  clk_cycle_count += 1;
+  
+  // Wire up outputs
+  return outputs;
+}

num_processes.cfg renamed to config/num_processes.cfg

@@ -1,5 +1 @@
-Tested with Vivado/Vitis tools version 2022.2
-
-Source Xilinx env first -> for example: "source /tools/Xilinx/Vitis/2022.2/settings64.sh"
-Use build_all.sh to build and run example project.
-If you wish to build for hw change target in build_all.sh script.
+See information on [wiki](github.com/JulianKemmerer/PipelineC/wiki/Vitis).

pipelinec_color.jpg renamed to docs/images/pipelinec_color.jpg

@@ -1,2 +1,3 @@
  #!/bin/bash
-../../src/pipelinec axis.c --out_dir OUT --coarse --sweep --start 100 --stop 100
+ # Must use default top module name = 'top' (same as --top top)
+../../src/pipelinec axis.c --out_dir OUT --xo_axis --coarse --sweep

examples/instance_array_fsms.c

@@ -1,8 +1,12 @@
 #!/bin/bash
+
+# Use ../build.sh to produce PipelineC ../OUT/package_axis_xo.tcl file
+
+# Vitis build steps:
 #TARGET=hw
 TARGET=hw_emu
 VITIS_PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1
-vivado -source sources/package_xo.tcl -mode batch
+vivado -source ../OUT/package_axis_xo.tcl -mode batch
 ./vitis_compile.sh ${TARGET} ${VITIS_PLATFORM}
 ./vitis_link.sh ${TARGET} ${VITIS_PLATFORM}
 ./gpp.sh

examples/vitis_import/README.txt

@@ -3,5 +3,5 @@ synth.jobs=4
 impl.jobs=12
 
 [connectivity]
-stream_connect=maxi_to_stream_1.output:my_ip_1.input_stream
-stream_connect=my_ip_1.output_stream:stream_to_maxi_1.input
+stream_connect=maxi_to_stream_1.output:top_ip_1.input_stream
+stream_connect=top_ip_1.output_stream:stream_to_maxi_1.input