Merge pull request #198 from JulianKemmerer/func_latency

Implement FUNC_LATENCY pragma for user defined pipeline building blocks

Author: JulianKemmerer

examples/user_func_latency.c

@@ -0,0 +1,83 @@
+
+
+#pragma PART "xc7a35ticsg324-1l"
+// How to allow user defined fixed pipeline latencies?
+// https://github.com/JulianKemmerer/PipelineC/issues/97
+#include "uintN_t.h"
+#include "compiler.h"
+
+/*
+#pragma FUNC_LATENCY small_op_delay 1
+uint64_t small_op_delay(uint64_t x){
+  static uint64_t the_reg;
+  uint64_t rv = the_reg;
+  the_reg = ~x;
+  return rv;
+}
+typedef struct values_t{
+  uint64_t user_delayed;
+  uint64_t tool_delayed;
+}values_t;
+#pragma MAIN_MHZ main 400.0
+values_t main(uint64_t x, uint64_t y){
+  values_t outputs;
+  outputs.tool_delayed = ~x + ~y;
+  outputs.user_delayed = small_op_delay(x) + small_op_delay(y);
+  return outputs;
+}
+*/
+
+BUILT_IN_RAM_FUNC_LATENCY(my_func, my_bram_RAM_DP_RF_1, 1)
+#pragma MAIN my_func
+uint32_t my_func(uint32_t waddr, uint32_t wdata, uint32_t raddr)
+{
+  static uint32_t my_bram[128];
+  //static uint32_t waddr = 0;
+  //static uint32_t wdata = 0;
+  //static uint32_t raddr = 0;
+  uint32_t rdata = my_bram_RAM_DP_RF_1(raddr, waddr, wdata, 1);
+  printf("Write: addr=%d,data=%d. Read addr=%d. Read data=%d\n",
+         waddr, wdata, raddr, rdata);
+  // Test pattern
+  //if(wdata > 0){
+  //  raddr += 1;
+  //}
+  //waddr += 1;
+  //wdata += 1;
+  return rdata; // Dummy
+}
+
+/*
+// This func is not allowed since it doesnt make sense in terms of implemented hardware
+// The static local variables describe clock by clock logic
+// but the BUILT_IN_RAM_FUNC_LATENCY=1 of my_bram_RAM_DP_RF_1 describes a pipeline
+#pragma MAIN my_bad_func
+BUILT_IN_RAM_FUNC_LATENCY(my_bad_func, my_bram_RAM_DP_RF_1, 1)
+uint32_t my_bad_func(uint32_t waddr, uint32_t wdata, uint32_t raddr)
+{
+  static uint32_t my_bram[128];
+  static uint32_t accum_rd_data = 0;
+  uint32_t rdata = my_bram_RAM_DP_RF_1(raddr, waddr, wdata, 1);
+  accum_rd_data += rdata;
+  return rdata + accum_rd_data;
+}
+*/
+/*
+#include "intN_t.h"
+#pragma FUNC_LATENCY one_cycle_negate 1
+int64_t one_cycle_negate(int64_t x){
+  static int64_t the_reg;
+  int64_t rv = the_reg;
+  the_reg = -x;
+  return rv;
+}
+#pragma MAIN_MHZ main 200.0
+// Output should always be == input after some cycles
+// But can be pipelined
+int64_t main(int64_t x){
+  int64_t nx = one_cycle_negate(x);
+  int64_t z = x + nx;
+  z = one_cycle_negate(z);
+  return z + x;
+}
+*/

pipelinec/include/compiler.h

@@ -80,6 +80,9 @@ PRAGMA_MESSAGE(MAIN_SYN_MHZ main_func mhz)
 #define MAIN_MHZ_GROUP(main_func, mhz, group)\
 PRAGMA_MESSAGE(MAIN_MHZ main_func mhz group)
 
+#define BUILT_IN_RAM_FUNC_LATENCY(call_location_func_name, ram_name, latency) \
+PRAGMA_MESSAGE(FUNC_LATENCY PPCAT(PPCAT(call_location_func_name,_),ram_name) latency)
+
 // Work around for user top level IO:
 // https://github.com/JulianKemmerer/PipelineC/issues/123
 // https://github.com/JulianKemmerer/PipelineC/issues/130

src/C_TO_LOGIC.py

@@ -737,6 +737,13 @@ def MERGE_COMB_LOGIC(self, logic_b):
             self.wire_driven_by, logic_b.wire_driven_by
         )
 
+        # Delay
+        if self.delay is not None and logic_b.delay is not None:
+            if self.delay != logic_b.delay:
+                raise Exception("Mismatch delay!")
+        elif self.delay is None:
+            self.delay = logic_b.delay
+
         # NExt user inst name?
         if self.next_user_inst_name != logic_b.next_user_inst_name:
             if self.next_user_inst_name is None:
@@ -1415,6 +1422,8 @@ def CAN_BE_SLICED(self, parser_state):
             return False
         return True
     def BODY_CAN_BE_SLICED(self, parser_state):
+        if self.func_name in parser_state.func_fixed_latency:
+            return False
         if not self.CAN_BE_SLICED(parser_state):
             return False
         if self.uses_nonvolatile_state_regs:
@@ -9605,7 +9614,7 @@ def DEL_ALL_CACHES():
     global _C_AST_REF_TOKS_TO_C_TYPE_cache
     global _C_AST_NODE_COORD_STR_cache
     global _C_AST_FUNC_DEF_TO_LOGIC_cache
-    # global _GET_ZERO_CLK_PIPELINE_MAP_cache
+    # global _GET_ZERO_ADDED_CLKS_PIPELINE_MAP_cache
 
     _other_partial_logic_cache = {}
     _REF_TOKS_TO_OWN_BRANCH_REF_TOKS_cache = {}
@@ -9617,7 +9626,7 @@ def DEL_ALL_CACHES():
     _C_AST_REF_TOKS_TO_C_TYPE_cache = {}
     _C_AST_NODE_COORD_STR_cache = {}
     _C_AST_FUNC_DEF_TO_LOGIC_cache = {}
-    # _GET_ZERO_CLK_PIPELINE_MAP_cache          = {}
+    # _GET_ZERO_ADDED_CLKS_PIPELINE_MAP_cache          = {}
 
 
 _EXE_ABS_DIR = None
@@ -9675,6 +9684,7 @@ def __init__(self):
         self.main_clk_group = {}  # dict[main_inst_name]=clk_group_str
         self.func_mult_style = {}
         self.func_marked_wires = set()
+        self.func_fixed_latency = {}
         self.func_marked_blackbox = set()
         self.func_marked_no_add_io_regs = set()
         self.func_marked_debug = set()
@@ -9737,6 +9747,7 @@ def DEEPCOPY(self):
         rv.main_clk_group = dict(self.main_clk_group)
         rv.func_mult_style = dict(self.func_mult_style)
         rv.func_marked_wires = set(self.func_marked_wires)
+        rv.func_fixed_latency = dict(self.func_fixed_latency)
         rv.func_marked_blackbox = set(self.func_marked_blackbox)
         rv.func_marked_no_add_io_regs = set(self.func_marked_no_add_io_regs)
         rv.func_marked_debug = set(self.func_marked_debug)
@@ -10198,32 +10209,32 @@ def PARSE_FILE(c_filename):
         sys.exit(-1)
 
 
-def WRITE_0CLK_FINAL_FILES(parser_state):
-    print("Building map of combinatorial logic...", flush=True)
+def WRITE_0_ADDED_CLKS_FINAL_FILES(parser_state):
+    print("Building map of logic to be pipelined...", flush=True)
     SYN.PART_SET_TOOL(
         parser_state.part, allow_fail=True
     )  # Comb logic only might not have tool set
-    ZeroClockTimingParamsLookupTable = SYN.GET_ZERO_CLK_TIMING_PARAMS_LOOKUP(
+    ZeroAddedClocksTimingParamsLookupTable = SYN.GET_ZERO_ADDED_CLKS_TIMING_PARAMS_LOOKUP(
         parser_state
     )
     multimain_timing_params = SYN.MultiMainTimingParams()
-    multimain_timing_params.TimingParamsLookupTable = ZeroClockTimingParamsLookupTable
+    multimain_timing_params.TimingParamsLookupTable = ZeroAddedClocksTimingParamsLookupTable
     # Write report of floating point module use - hi Victor!
     WRITE_FLOAT_MODULE_INSTANCES_REPORT(multimain_timing_params, parser_state)
     # Integers too..
     WRITE_INTEGER_MODULE_INSTANCES_REPORT(multimain_timing_params, parser_state)
     print(
-        "Writing VHDL files for all functions (as combinatorial logic)...", flush=True
+        "Writing VHDL files for all functions (before any added pipelining)...", flush=True
     )
-    SYN.WRITE_ALL_ZERO_CLK_VHDL(parser_state, ZeroClockTimingParamsLookupTable)
+    SYN.WRITE_ALL_ZERO_CLK_VHDL(parser_state, ZeroAddedClocksTimingParamsLookupTable)
     print(
         "Writing the constant struct+enum definitions as defined from C code...",
         flush=True,
     )
     VHDL.WRITE_C_DEFINED_VHDL_STRUCTS_PACKAGE(parser_state)
     print("Writing global wire definitions as parsed from C code...", flush=True)
     VHDL.WRITE_GLOBAL_WIRES_VHDL_PACKAGE(parser_state)
-    print("Writing finalized comb. logic synthesis tool files...", flush=True)
+    print("Writing output files before adding pipelining...", flush=True)
     SYN.WRITE_FINAL_FILES(multimain_timing_params, parser_state)
 
 
@@ -11568,6 +11579,13 @@ def APPEND_PRAGMA_INFO(parser_state):
             main_func = toks[1]
             parser_state.func_marked_wires.add(main_func)
 
+        # FUNC_LATENCY
+        elif name == "FUNC_LATENCY":
+            toks = pragma.string.split(" ")
+            func = toks[1]
+            latency = int(toks[2])
+            parser_state.func_fixed_latency[func] = latency
+
         # FUNC_BLACKBOX
         elif name == "FUNC_BLACKBOX":
             toks = pragma.string.split(" ")

src/SW_LIB.py

@@ -1855,12 +1855,31 @@ def GET_MEM_NAME(logic):
         return RAM_SP_RF + "_2"
     elif logic.func_name.endswith("_" + RAM_DP_RF + "_0"):
         return RAM_DP_RF + "_0"
+    elif logic.func_name.endswith("_" + RAM_DP_RF + "_1"):
+        return RAM_DP_RF + "_1"
     elif logic.func_name.endswith("_" + RAM_DP_RF + "_2"):
         return RAM_DP_RF + "_2"
     else:
         print("GET_MEM_NAME for func", logic.func_name, "?")
         sys.exit(-1)
 
+def MEM_NAME_TO_LATENCY(mem_name):
+    if mem_name == RAM_SP_RF + "_0":
+        return 0
+    elif mem_name ==  RAM_SP_RF + "_1":
+        return 1
+    elif mem_name ==  RAM_SP_RF + "_2":
+        return 2
+    elif mem_name ==  RAM_DP_RF + "_0":
+        return 0
+    elif mem_name ==  RAM_DP_RF + "_1":
+        return 1
+    elif mem_name ==  RAM_DP_RF + "_2":
+        return 2
+    else:
+        print("MEM_NAME_TO_LATENCY for mem_name", mem_name, "?")
+        sys.exit(-1)
+
 
 def GET_BIT_MATH_H_LOGIC_LOOKUP_FROM_FUNC_NAMES(func_names, parser_state):
     # TODO dont do string search at all - do 'in' list checks?