Implement support for async fifo that doesnt use manufacturer ip, thanks Alex

Author: JulianKemmerer

examples/async_clock_crossing.c

@@ -1,11 +1,12 @@
 // Similar to clock_crossing.c except that instead of 
 // data width integer ratioed clock crossing stream,
 // this uses same size read and write ports on an async fifo
-
+//#pragma PART "xc7a35ticsg324-1l" // Artix 7 35T (Arty)
+#pragma PART "LFE5U-85F-6BG381C"
 #include "uintN_t.h"
 #include "leds/led0_3_ports.c"
 
-#pragma MAIN_MHZ fast 166.66
+#pragma MAIN_MHZ fast 40.0
 #pragma MAIN_MHZ slow 25.0
 
 // Write+read 2 'datas' in/out the fifo at a time
@@ -28,8 +29,9 @@ ASYNC_CLK_CROSSING_WIDTH_DEPTH(data_t, fast_to_slow, DATAS_PER_ITER, 4)
 //#include "clock_crossing/slow_to_fast.h" // Auto generated
 ASYNC_CLK_CROSSING_WIDTH_DEPTH(data_t, slow_to_fast, DATAS_PER_ITER, 4)
 
-void fast(uint1_t reset)
+void fast() 
 {  
+  uint1_t reset = 0; // No reset for now
   // Drive leds with state, default lit
   static uint1_t test_failed = 0;
   uint1_t led = 1;
@@ -57,7 +59,7 @@ void fast(uint1_t reset)
   }
   fast_to_slow_write_t write = fast_to_slow_WRITE_N(wr_data, wr_en);
   // Did the write go through?
-  if(write.ready)
+  if(wr_en & write.ready)
   {
     // Next test data
     test_data += DATAS_PER_ITER;
@@ -77,7 +79,7 @@ void fast(uint1_t reset)
   {
     rd_en = 0;
   }
-  // Try to read 1 data element from the fifo
+  // Try to read N data elements from the fifo
   slow_to_fast_read_t read = slow_to_fast_READ_N(rd_en);
   // Did the read go through
   if(rd_en & read.valid)
@@ -104,8 +106,9 @@ void fast(uint1_t reset)
   }
 }
 
-void slow(uint1_t reset)
+void slow()
 {
+  uint1_t reset = 0; // No reset for now
   // Drive leds with state, default lit
   static uint1_t test_failed = 0;
   uint1_t led = 1;
@@ -133,7 +136,7 @@ void slow(uint1_t reset)
   }
   slow_to_fast_write_t write = slow_to_fast_WRITE_N(wr_data, wr_en);
   // Did the write go through?
-  if(write.ready)
+  if(wr_en & write.ready)
   {
     // Next test data
     test_data += DATAS_PER_ITER;
@@ -153,7 +156,7 @@ void slow(uint1_t reset)
   {
     rd_en = 0;
   }
-  // Try to read 1 data element from the fifo
+  // Try to read N data elements from the fifo
   fast_to_slow_read_t read = fast_to_slow_READ_N(rd_en);
   // Did the read go through
   if(rd_en & read.valid)

src/SYN.py

@@ -4985,6 +4985,7 @@ def GET_VHDL_FILES_TCL_TEXT_AND_TOP(
 
     # Built in src/vhdl #TODO just auto add every file in dir
     files_txt += SYN_OUTPUT_DIRECTORY + "/" + "built_in/pipelinec_fifo_fwft.vhd" + " "
+    files_txt += SYN_OUTPUT_DIRECTORY + "/" + "built_in/pipelinec_async_fifo_fwft.vhd" + " "
 
     # C defined structs
     files_txt += SYN_OUTPUT_DIRECTORY + "/" + "c_structs_pkg" + VHDL.VHDL_PKG_EXT + " "

src/VHDL.py

@@ -2673,6 +2673,9 @@ def WRITE_CLK_CROSS_ENTITIES(parser_state, multimain_timing_params):
             clk_ext_strs.add(clk_ext_str_i)
         if len(clk_ext_strs) > 1:
             flow_control_is_async = True
+            # Need to know syn tool for what type of CDC to render
+            if SYN.SYN_TOOL is None:
+                SYN.PART_SET_TOOL(parser_state.part)
         write_size, read_size = parser_state.clk_cross_var_info[
             var_name
         ].write_read_sizes
@@ -2688,13 +2691,6 @@ def WRITE_CLK_CROSS_ENTITIES(parser_state, multimain_timing_params):
 
         # TODO OTHER SIZES
         if flow_control:
-            if SYN.SYN_TOOL is None:
-                SYN.PART_SET_TOOL(parser_state.part)
-            if flow_control_is_async and SYN.SYN_TOOL is not VIVADO:
-                raise Exception(
-                    "Async fifos are only implemented for Xilinx parts, TODO!", var_name
-                )
-
             if write_size != read_size:
                 raise Exception(
                     "Only equal read and write sizes for async fifos for now, TODO!",
@@ -2729,7 +2725,7 @@ def WRITE_CLK_CROSS_ENTITIES(parser_state, multimain_timing_params):
                 print("More than 1 dim for async flow control!?", var_name)
                 sys.exit(-1)
             depth = dims[0]
-            if flow_control_is_async and depth < 16:
+            if flow_control_is_async and SYN.SYN_TOOL is VIVADO and depth < 16:
                 depth = 16
                 print(
                     "WARNING:",
@@ -2749,7 +2745,7 @@ def WRITE_CLK_CROSS_ENTITIES(parser_state, multimain_timing_params):
 use work.c_structs_pkg.all; -- User types
 """
 
-        if flow_control and flow_control_is_async:
+        if flow_control and flow_control_is_async and SYN.SYN_TOOL is VIVADO:
             text += """
 library xpm;
 use xpm.vcomponents.all;
@@ -2938,7 +2934,7 @@ def WRITE_CLK_CROSS_ENTITIES(parser_state, multimain_timing_params):
                 + """dout_slv"""
                 + from_slv_toks[1]
                 + """;""")
-        if flow_control and flow_control_is_async:
+        if flow_control and flow_control_is_async and SYN.SYN_TOOL is VIVADO:
             text += (
                 """
 wr_power_on_reset <= '0' when rising_edge(in_clk);
@@ -3079,21 +3075,34 @@ def WRITE_CLK_CROSS_ENTITIES(parser_state, multimain_timing_params):
 -- End of xpm_fifo_async_inst instantiation     
 """
             )
-
-        # Sync built in fifo
-        elif flow_control and not flow_control_is_async:
+        # Built in fifo sync or async looks similar
+        elif flow_control:
+            text += """
+pipelinec_fifo_fwft_inst : entity work."""
+            if not flow_control_is_async:
+                text += "pipelinec_fifo_fwft"
+            else:
+                text += "pipelinec_async_fifo_fwft"
             text += """
-pipelinec_fifo_fwft_inst : entity work.pipelinec_fifo_fwft
 generic map (
     DEPTH_LOG2 => """ + str(math.ceil(math.log(depth, 2))) + """,
     DATA_WIDTH => """ + C_TYPE_STR_TO_VHDL_SLV_LEN_STR(in_t, parser_state) + """
 )
 port map
 (
-    clk => in_clk,
+"""
+            if flow_control_is_async:
+                text += "    in_clk => in_clk,\n"
+            else:
+                text += "    clk => in_clk,\n"
+            text += """
     valid_in  => write_enable(0) and in_clk_en(0),
     ready_out => wr_return_output.ready(0),
     data_in   => din_slv,
+    """
+            if flow_control_is_async:
+                text += "    out_clk => out_clk,\n"
+            text += """
     valid_out => rd_return_output.valid(0),
     ready_in  => read_enable(0) and out_clk_en(0),
     data_out  => dout_slv