Vitis

WORK IN PROGRESS

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This page describes the current state of PipelineC+Xilinx Vitis integration.

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Beginning in PR 127, the primary person behind this fantastic work is @bartokon. If you have any Vitis-related questions or comments they are likely the best person to contact.

The files discussed here are in the PipelineC repo at examples/vitis_import.

Files

• axis.c: PipelineC main file
  • Pipeline the_pipeline()
    • Function is autopipelined to meet MAIN_MHZ specified
    • Has input and output wires connected to the IO and Control logic
  • IO and Control io_and_ctrl()
    • Has wires to and from the pipeline
    • Inputs go directly into pipeline
    • After being output from the pipeline, output data is stored in FIFO
    • Output data FIFO is used to ready data out as out_ready is signaled
• build.sh: script to run pipelinec tool and produce VHDL
• vitis_scripts: All Vitis files

Build

These scripts are used to generate Vitis HLS IP's that transfer data to/from PipelineC generated IP. 
Streaming interfaces are used as communication channel. PipelineC IP is packaged as .XO and connected with Vitis at linking stage.

Tested with Vivado/Vitis tools version 2022.2

Source Xilinx env first -> for example: "source /tools/Xilinx/Vitis/2022.2/settings64.sh"
Use build_all.sh to build and run example project.
If you wish to build for hw change target in build_all.sh script.

Software Emulation

sw_emu

Hardware Emulation (Simulation)

hw_emu

Hardware Test

TODO