The proposed encoding scheme for the circuit would be:
- 31-28:
OPCODE - 27-24:
RY - 23-20:
RA - 19-16:
RB - 15-00:
Immediate
The instuction set needed to define for the processor are
MOV RA RB: Content of RB is transferred to RAMVI RA Im: The Immediate value Im is stored in RALOAD RA RB X: The content of the memory location [[RB]+X] is loaded into RA, where X is a 16bit unsigned immediate valueSTORE RA RB X: The content of register RA is stored in memory location [[RB]+X] where X is again, a 16bit unsigned immediate valueADD RA RB RC: RA = RB + RCADI RA RB Im: RA = RB + Im, where Im is a 32-bit unsigned extended immediate valueSUB RA RB RC: RA = RB - RCSUI RA RB Im: RA = RB - Im, where Im is a 32-bit unsigned extended immediate valueAND RA RB RC: RA = RB AND RCANI RA RB IM: RA = RB AND Im, where Im is a 32-bit unsigned extended immediate valueOR RA RB RC: RA = RB OR RCORI RA RB IM: RA = RB OR Im, where Im is a 32-bit unsigned extended immediate valueHLT: Stops the Execution at current address
The OPCODES FOR THE OPERATIONS ARE WITH ALU MAPPING :
ADD: 0000 (0) (SUM)ADI: 0001 (1) (SUM)SUB: 0010 (2) (DIFF)SUI: 0011 (3) (DIFF)AND: 0100 (4) (AND)ANI: 0101 (5) (AND)OR: 0110 (6) (OR)ORI: 0111 (7) (OR)MOV: 1000 (8) (RA)MVI: 1001 (9) (RB)LOAD: 1010 (10) (SUM)STORE: 1011 (11) (SUM)HLT: 1111 (15) (NOP)
There are 8 registers available, those are:
R1: 000R2: 001R3: 010R4: 011R5: 100R6: 101R7: 110R8: 111
NOTE: The immediate values are 16-bit
NOTE: The entirety of OPCODE is ALU_SELECT
- All literals are expected to be in hexadecimal, if not found, they are converted into hex.
- All immediate values would be capped at 16 bit
For example the instruction
ADI R2 R1 56
would translate to:
0010 0001 0000 0000 0000000000111000
0010 0001 0000 0000 0000 0000 0011 1000
And converting into hex, we have
