[Backport to llvm_release_110] Implement SPV_INTEL_sigmoid extension (#3432)

Spec link: intel/llvm#20504

Author: vsemenov368

include/LLVMSPIRVExtensions.inc

@@ -51,3 +51,4 @@ EXT(SPV_INTEL_global_variable_decorations)
 EXT(SPV_INTEL_maximum_registers)
 EXT(SPV_KHR_bfloat16)
 EXT(SPV_INTEL_bfloat16_arithmetic)
+EXT(SPV_INTEL_sigmoid)

lib/SPIRV/libSPIRV/SPIRVInstruction.h

@@ -3579,5 +3579,63 @@ template <Op OC> class SPIRVReadClockKHRInstBase : public SPIRVUnaryInst<OC> {
 _SPIRV_OP(ReadClockKHR)
 #undef _SPIRV_OP
 
+template <Op OC> class SPIRVFSigmoidINTELInstBase : public SPIRVUnaryInst<OC> {
+protected:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(internal::CapabilitySigmoidINTEL);
+  }
+
+  llvm::Optional<ExtensionID> getRequiredExtension() const override {
+    return ExtensionID::SPV_INTEL_sigmoid;
+  }
+
+  void validate() const override {
+    SPIRVUnaryInst<OC>::validate();
+
+    SPIRVType *ResCompTy = this->getType();
+    SPIRVWord ResCompCount = 1;
+    if (ResCompTy->isTypeVector()) {
+      ResCompCount = ResCompTy->getVectorComponentCount();
+      ResCompTy = ResCompTy->getVectorComponentType();
+    }
+
+    // validate is a const method, whilst getOperand is non-const method
+    // because it may call a method of class Module that may modify LiteralMap
+    // of Module field. That modification is not impacting validate method for
+    // these instructions, so const_cast is safe here.
+    using SPVFSigmoidTy = SPIRVFSigmoidINTELInstBase<OC>;
+    const SPIRVValue *Input = const_cast<SPVFSigmoidTy *>(this)->getOperand(0);
+
+    SPIRVType *InCompTy = Input->getType();
+    SPIRVWord InCompCount = 1;
+    if (InCompTy->isTypeVector()) {
+      InCompCount = InCompTy->getVectorComponentCount();
+      InCompTy = InCompTy->getVectorComponentType();
+    }
+
+    auto InstName = OpCodeNameMap::map(OC);
+    SPIRVErrorLog &SPVErrLog = this->getModule()->getErrorLog();
+
+    SPVErrLog.checkError(
+        ResCompTy->isTypeFloat(16) || ResCompTy->isTypeFloat(32) ||
+            ResCompTy->isTypeFloat(16, FPEncodingBFloat16KHR),
+        SPIRVEC_InvalidInstruction,
+        InstName + "\nResult value must be a scalar or vector of floating-point"
+                   " 16-bit or 32-bit type\n");
+    SPVErrLog.checkError(
+        ResCompTy == InCompTy, SPIRVEC_InvalidInstruction,
+        InstName +
+            "\nInput type must have the same component type as result type\n");
+    SPVErrLog.checkError(
+        ResCompCount == InCompCount, SPIRVEC_InvalidInstruction,
+        InstName + "\nInput type must have the same number of components as "
+                   "result type\n");
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVFSigmoidINTELInstBase<internal::Op##x> SPIRV##x;
+_SPIRV_OP(FSigmoidINTEL)
+#undef _SPIRV_OP
 } // namespace SPIRV
 #endif // SPIRV_LIBSPIRV_SPIRVINSTRUCTION_H

lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

@@ -586,6 +586,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(internal::CapabilityGlobalVariableDecorationsINTEL,
       "GlobalVariableDecorationsINTEL");
   add(internal::CapabilityBFloat16ArithmeticINTEL, "BFloat16ArithmeticINTEL");
+  add(internal::CapabilitySigmoidINTEL, "SigmoidINTEL");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 

lib/SPIRV/libSPIRV/SPIRVOpCodeEnumInternal.h

@@ -9,3 +9,4 @@ _SPIRV_OP_INTERNAL(ConvertBF16ToFINTEL, internal::OpConvertBF16ToFINTEL)
 _SPIRV_OP_INTERNAL(MaskedGatherINTEL, internal::OpMaskedGatherINTEL)
 _SPIRV_OP_INTERNAL(MaskedScatterINTEL, internal::OpMaskedScatterINTEL)
 _SPIRV_OP_INTERNAL(RoundFToTF32INTEL, internal::RoundFToTF32INTEL)
+_SPIRV_OP_INTERNAL(FSigmoidINTEL, internal::FSigmoidINTEL)

lib/SPIRV/libSPIRV/spirv_internal.hpp

@@ -43,6 +43,7 @@ enum InternalOp {
   IOpRoundFToTF32INTEL = 6426,
   IOpMaskedGatherINTEL = 6428,
   IOpMaskedScatterINTEL = 6429,
+  IOpFSigmoidINTEL = 6168,
   IOpPrev = OpMax - 2,
   IOpForward
 };
@@ -61,6 +62,7 @@ enum InternalCapability {
   ICapDebugInfoModuleINTEL = 6114,
   ICapBfloat16ConversionINTEL = 6115,
   ICapabilityBFloat16ArithmeticINTEL = 6226,
+  ICapabilitySigmoidINTEL = 6167,
   ICapabilityTensorFloat32RoundingINTEL = 6425,
   ICapabilityMaskedGatherScatterINTEL = 6427,
   ICapabilityHWThreadQueryINTEL = 6134,
@@ -87,6 +89,8 @@ enum InternalBuiltIn {
 _SPIRV_OP(Capability, HWThreadQueryINTEL)
 _SPIRV_OP(BuiltIn, SubDeviceIDINTEL)
 _SPIRV_OP(BuiltIn, GlobalHWThreadIDINTEL)
+_SPIRV_OP(Capability, SigmoidINTEL)
+_SPIRV_OP(Op, FSigmoidINTEL)
 #undef _SPIRV_OP
 
 constexpr Op OpForward = static_cast<Op>(IOpForward);

test/extensions/INTEL/SPV_INTEL_sigmoid/sigmoid_f16.ll

@@ -0,0 +1,50 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_sigmoid
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
+; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+
+; RUN: not llvm-spirv %t.bc 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension:
+; CHECK-ERROR-NEXT: SPV_INTEL_sigmoid
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-unknown"
+
+; CHECK-SPIRV: Capability SigmoidINTEL
+; CHECK-SPIRV: Extension "SPV_INTEL_sigmoid"
+; CHECK-SPIRV: TypeFloat [[#FP16Ty:]] 16
+; CHECK-SPIRV: TypeVector [[#FP16v8Ty:]] [[#FP16Ty]] 8
+; CHECK-SPIRV: Constant [[#FP16Ty]] [[#CONST:]] 15360
+
+; CHECK-SPIRV: FunctionParameter [[#FP16Ty]] [[FP16ValId:.*]]
+; CHECK-SPIRV: FunctionParameter [[#FP16v8Ty]] [[FP16v8ValId:.*]]
+
+; CHECK-SPIRV: FSigmoidINTEL [[#FP16Ty]] [[#]] [[FP16ValId]]
+; CHECK-SPIRV: FSigmoidINTEL [[#FP16v8Ty]] [[#]] [[FP16v8ValId]]
+; CHECK-SPIRV: FSigmoidINTEL [[#FP16Ty]] [[#]] [[#CONST]]
+
+; CHECK-LLVM: call spir_func half @_Z21__spirv_FSigmoidINTELDh(half
+; CHECK-LLVM: call spir_func <8 x half> @_Z21__spirv_FSigmoidINTELDv8_Dh(<8 x half>
+; CHECK-LLVM: call spir_func half @_Z21__spirv_FSigmoidINTELDh(half 0xH3C00)
+
+define spir_func void @_Z2opffv8(half %a, <8 x half> %in) {
+  %1 = tail call spir_func half @_Z21__spirv_FSigmoidINTELDh(half %a)
+  %2 = tail call spir_func <8 x half> @_Z21__spirv_FSigmoidINTELDv8_Dh(<8 x half> %in)
+  %3 = tail call spir_func half @_Z21__spirv_FSigmoidINTELDh(half 1.000000e+00)
+  ret void
+}
+
+declare spir_func half @_Z21__spirv_FSigmoidINTELDh(half)
+
+declare spir_func <8 x half> @_Z21__spirv_FSigmoidINTELDv8_Dh(<8 x half>)
+
+!opencl.spir.version = !{!0}
+!spirv.Source = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, i32 2}
+!1 = !{i32 4, i32 100000}
+!2 = !{!"clang version 16.0.0"}

test/extensions/INTEL/SPV_INTEL_sigmoid/sigmoid_f32.ll

@@ -0,0 +1,50 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_sigmoid
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
+; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+
+; RUN: not llvm-spirv %t.bc 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension:
+; CHECK-ERROR-NEXT: SPV_INTEL_sigmoid
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-unknown"
+
+; CHECK-SPIRV: Capability SigmoidINTEL
+; CHECK-SPIRV: Extension "SPV_INTEL_sigmoid"
+; CHECK-SPIRV: TypeFloat [[#FP32Ty:]] 32
+; CHECK-SPIRV: TypeVector [[#FP32v8Ty:]] [[#FP32Ty]] 8
+; CHECK-SPIRV: Constant [[#FP32Ty]] [[#CONST:]] 1065353216
+
+; CHECK-SPIRV: FunctionParameter [[#FP32Ty]] [[FP32ValId:.*]]
+; CHECK-SPIRV: FunctionParameter [[#FP32v8Ty]] [[FP32v8ValId:.*]]
+
+; CHECK-SPIRV: FSigmoidINTEL [[#FP32Ty]] [[#]] [[FP32ValId]]
+; CHECK-SPIRV: FSigmoidINTEL [[#FP32v8Ty]] [[#]] [[FP32v8ValId]]
+; CHECK-SPIRV: FSigmoidINTEL [[#FP32Ty]] [[#]] [[#CONST]]
+
+; CHECK-LLVM: call spir_func float @_Z21__spirv_FSigmoidINTELf(float
+; CHECK-LLVM: call spir_func <8 x float> @_Z21__spirv_FSigmoidINTELDv8_f(<8 x float>
+; CHECK-LLVM: call spir_func float @_Z21__spirv_FSigmoidINTELf(float 1.000000e+00)
+
+define spir_func void @_Z2opffv8(float %a, <8 x float> %in) {
+  %1 = tail call spir_func float @_Z21__spirv_FSigmoidINTELf(float %a)
+  %2 = tail call spir_func <8 x float> @_Z21__spirv_FSigmoidINTELDv8_f(<8 x float> %in)
+  %3 = tail call spir_func float @_Z21__spirv_FSigmoidINTELf(float 1.000000e+00)
+  ret void
+}
+
+declare spir_func float @_Z21__spirv_FSigmoidINTELf(float)
+
+declare spir_func <8 x float> @_Z21__spirv_FSigmoidINTELDv8_f(<8 x float>)
+
+!opencl.spir.version = !{!0}
+!spirv.Source = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, i32 2}
+!1 = !{i32 4, i32 100000}
+!2 = !{!"clang version 16.0.0"}