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Regularize LLVM code to remove use of non standard integer types in fptoui and fptosi intrinsics (#2500)
* Regularize LLVM code to remove use of non standard integer types in fptoui and fptosi intrinsics Signed-off-by: Sudarsanam, Arvind <[email protected]>
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‎lib/SPIRV/SPIRVRegularizeLLVM.cpp‎

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@@ -322,6 +322,104 @@ void SPIRVRegularizeLLVMBase::expandSYCLTypeUsing(Module *M) {
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expandVIDWithSYCLTypeByValComp(F);
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}
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// In this function, we handle two conversion operations
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// 1. fptoui.sat.iX.fY (X is not 8,16,32,64; Y is 32 or 64)
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// 2. fptosi.sat.iX.fY (X is not 8,16,32,64; Y is 32 or 64)
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// Such non-standard integer types cannot be handled in SPIR-V. Hence, they
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// will be promoted to
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// 1. fptoui.sat.i64.fY (Y is 32 or 64)
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// 2. fptosi.sat.i64.fY (Y is 32 or 64)
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// However, LLVM documentation requires the following rules to be obeyed.
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// Rule 1: If the argument is any NaN, zero is returned.
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// Rule 2: If the argument is smaller than the smallest representable
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// (un)signed integer of the result type, the smallest representable
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// (un)signed integer is returned.
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// Rule 3: If the argument is larger than the largest representable (un)signed
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// integer of the result type, the largest representable (un)signed integer is
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// returned.
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// Rule 4: Otherwise, the result of rounding the argument towards zero is
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// returned.
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// Rules 1 & 4 are preserved when promoting iX to i64. For preserving Rule 2
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// and Rule 3, we saturate the result of the promoted instruction based on
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// original integer type (iX)
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// Example:
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// Input:
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// %0 = call i2 @llvm.fptosi.sat.i2.f32(float %input)
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// %1 = sext i32 %0
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// Output:
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// %0 = call i32 @_Z17convert_long_satf(float %input)
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// %1 = icmp sge i32 %0, 1 <Largest 2-bit signed integer>
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// %2 = icmp sle i32 %0, -2 <Smallest 2-bit signed integer>
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// %3 = select i1 %1, i32 1, i32 %0
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// %4 = select i1 %2, i32 -2, i32 %3
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// Replace uses of %1 in Input with %4 in Output
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void SPIRVRegularizeLLVMBase::cleanupConversionToNonStdIntegers(Module *M) {
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for (auto FI = M->begin(), FE = M->end(); FI != FE;) {
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Function *F = &(*FI++);
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std::vector<Instruction *> ToErase;
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auto IID = F->getIntrinsicID();
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if (IID != Intrinsic::fptosi_sat && IID != Intrinsic::fptoui_sat)
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continue;
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for (auto *I : F->users()) {
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if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
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// TODO: Vector type not supported yet.
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if (isa<VectorType>(II->getType()))
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continue;
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auto IID = II->getIntrinsicID();
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auto IntBitWidth = II->getType()->getScalarSizeInBits();
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if (IntBitWidth == 8 || IntBitWidth == 16 || IntBitWidth == 32 ||
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IntBitWidth == 64)
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continue;
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if (IID == Intrinsic::fptosi_sat) {
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// Identify sext (user of II). Make sure that's the only use of II.
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auto *User = II->getUniqueUndroppableUser();
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if (!User || !isa<SExtInst>(User))
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continue;
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auto *SExtI = dyn_cast<SExtInst>(User);
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auto *NewIType = SExtI->getType();
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IRBuilder<> IRB(II);
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auto *NewII = IRB.CreateIntrinsic(
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IID, {NewIType, II->getOperand(0)->getType()}, II->getOperand(0));
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Constant *MaxVal = ConstantInt::get(
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NewIType, APInt::getSignedMaxValue(IntBitWidth).getSExtValue());
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Constant *MinVal = ConstantInt::get(
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NewIType, APInt::getSignedMinValue(IntBitWidth).getSExtValue());
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auto *GTMax = IRB.CreateICmp(CmpInst::ICMP_SGE, NewII, MaxVal);
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auto *LTMin = IRB.CreateICmp(CmpInst::ICMP_SLE, NewII, MinVal);
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auto *SatMax = IRB.CreateSelect(GTMax, MaxVal, NewII);
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auto *SatMin = IRB.CreateSelect(LTMin, MinVal, SatMax);
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SExtI->replaceAllUsesWith(SatMin);
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ToErase.push_back(SExtI);
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ToErase.push_back(II);
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}
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if (IID == Intrinsic::fptoui_sat) {
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// Identify zext (user of II). Make sure that's the only use of II.
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auto *User = II->getUniqueUndroppableUser();
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if (!User || !isa<ZExtInst>(User))
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continue;
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auto *ZExtI = dyn_cast<ZExtInst>(User);
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auto *NewIType = ZExtI->getType();
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IRBuilder<> IRB(II);
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auto *NewII = IRB.CreateIntrinsic(
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IID, {NewIType, II->getOperand(0)->getType()}, II->getOperand(0));
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Constant *MaxVal = ConstantInt::get(
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NewIType, APInt::getMaxValue(IntBitWidth).getZExtValue());
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auto *GTMax = IRB.CreateICmp(CmpInst::ICMP_UGE, NewII, MaxVal);
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auto *SatMax = IRB.CreateSelect(GTMax, MaxVal, NewII);
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ZExtI->replaceAllUsesWith(SatMax);
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ToErase.push_back(ZExtI);
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ToErase.push_back(II);
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}
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}
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}
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for (Instruction *V : ToErase) {
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assert(V->user_empty());
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V->dropAllReferences();
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V->eraseFromParent();
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}
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}
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}
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bool SPIRVRegularizeLLVMBase::runRegularizeLLVM(Module &Module) {
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M = &Module;
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Ctx = &M->getContext();
@@ -404,6 +502,7 @@ bool SPIRVRegularizeLLVMBase::regularize() {
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eraseUselessFunctions(M);
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addKernelEntryPoint(M);
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expandSYCLTypeUsing(M);
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cleanupConversionToNonStdIntegers(M);
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for (auto I = M->begin(), E = M->end(); I != E;) {
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Function *F = &(*I++);

‎lib/SPIRV/SPIRVRegularizeLLVM.h‎

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@@ -96,6 +96,12 @@ class SPIRVRegularizeLLVMBase {
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void expandVEDWithSYCLTypeSRetArg(llvm::Function *F);
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void expandVIDWithSYCLTypeByValComp(llvm::Function *F);
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// It is possible that incoming LLVM IR conversion instructions convert
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// floating point to non-standard integer types. Such types are not supported
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// in SPIR-V. This function cleans up such code and removes occurence of
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// non-standard integer types.
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void cleanupConversionToNonStdIntegers(llvm::Module *M);
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// According to the specification, the operands of a shift instruction must be
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// a scalar/vector of integer. When LLVM-IR contains a shift instruction with
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// i1 operands, they are treated as a bool. We need to extend them to i32 to

‎test/llvm-intrinsics/fp_to_arbitrary_size_int_intrinsic.ll‎

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;; Ensure @llvm.fptosi.sat.* and @llvm.fptoui.sat.* intrinsics are translated
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; RUN: llvm-as %s -o %t.bc
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; RUN: llvm-spirv %t.bc -spirv-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; RUN: llvm-spirv %t.bc -o %t.spv
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; RUN: spirv-val %t.spv
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; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
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; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
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target triple = "spir64-unknown-unknown"
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; CHECK-SPIRV-DAG: Capability Kernel
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; CHECK-SPIRV-DAG: Decorate [[SAT1:[0-9]+]] SaturatedConversion
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; CHECK-SPIRV-DAG: Decorate [[SAT2:[0-9]+]] SaturatedConversion
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; CHECK-SPIRV-DAG: TypeInt [[INT64TY:[0-9]+]] 64
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; CHECK-SPIRV-DAG: TypeBool [[BOOLTY:[0-9]+]]
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; CHECK-SPIRV-DAG: Constant [[INT64TY]] [[I2SMAX:[0-9]+]] 1
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; CHECK-SPIRV-DAG: Constant [[INT64TY]] [[I2SMIN:[0-9]+]] 4294967294
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; CHECK-SPIRV-DAG: ConvertFToS [[INT64TY]] [[SAT1]]
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; CHECK-SPIRV-DAG: SGreaterThanEqual [[BOOLTY]] [[SGERES:[0-9]+]] [[SAT1]] [[I2SMAX]]
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; CHECK-SPIRV-DAG: SLessThanEqual [[BOOLTY]] [[SLERES:[0-9]+]] [[SAT1]] [[I2SMIN]]
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; CHECK-SPIRV-DAG: Select [[INT64TY]] [[SELRES1:[0-9]+]] [[SGERES]] [[I2SMAX]] [[SAT1]]
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; CHECK-SPIRV-DAG: Select [[INT64TY]] [[SELRES2:[0-9]+]] [[SLERES]] [[I2SMIN]] [[SELRES1]]
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; CHECK-LLVM-DAG: define spir_kernel
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; CHECK-LLVM-DAG: %[[R1:[0-9]+]] = {{.*}} i64 {{.*}}convert_long_satf(float %input)
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; CHECK-LLVM-DAG: %[[R2:[0-9]+]] = icmp sge i64 %[[R1]], 1
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; CHECK-LLVM-DAG: %[[R3:[0-9]+]] = icmp sle i64 %[[R1]], -2
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; CHECK-LLVM-DAG: %[[R4:[0-9]+]] = select i1 %[[R2]], i64 1, i64 %[[R1]]
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; CHECK-LLVM-DAG: %[[R5:[0-9]+]] = select i1 %[[R3]], i64 -2, i64 %[[R4]]
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define spir_kernel void @testfunction_float_to_signed_i2(float %input) {
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entry:
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%0 = call i2 @llvm.fptosi.sat.i2.f32(float %input)
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%1 = sext i2 %0 to i64
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ret void
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}
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declare i2 @llvm.fptosi.sat.i2.f32(float)
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; CHECK-SPIRV-DAG: Constant [[INT64TY]] [[I2UMAX:[0-9]+]] 3
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; CHECK-SPIRV-DAG: ConvertFToU [[INT64TY]] [[SAT2]]
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; CHECK-SPIRV-DAG: UGreaterThanEqual [[BOOLTY]] [[UGERES:[0-9]+]] [[SAT2]] [[I2UMAX]]
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; CHECK-SPIRV-DAG: Select [[INT64TY]] [[SELRES1U:[0-9]+]] [[UGERES]] [[I2UMAX]] [[SAT2]]
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; CHECK-LLVM-DAG: define spir_kernel
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; CHECK-LLVM-DAG: %[[R1:[0-9]+]] = {{.*}} i64 {{.*}}convert_ulong_satf(float %input)
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; CHECK-LLVM-DAG: %[[R2:[0-9]+]] = icmp uge i64 %[[R1]], 3
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; CHECK-LLVM-DAG: %[[R3:[0-9]+]] = select i1 %[[R2]], i64 3, i64 %[[R1]]
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define spir_kernel void @testfunction_float_to_unsigned_i2(float %input) {
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entry:
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%0 = call i2 @llvm.fptoui.sat.i2.f32(float %input)
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%1 = zext i2 %0 to i64
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ret void
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}
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declare i2 @llvm.fptoui.sat.i2.f32(float)

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