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| 1 | +//===- SPIRVAsm.h - --*- C++ -*-===// |
| 2 | +// |
| 3 | +// The LLVM/SPIRV Translator |
| 4 | +// |
| 5 | +// This file is distributed under the University of Illinois Open Source |
| 6 | +// License. See LICENSE.TXT for details. |
| 7 | +// |
| 8 | +//===----------------------------------------------------------------------===// |
| 9 | +/// \file |
| 10 | +/// |
| 11 | +/// This file defines the inline assembler entries defined in SPIRV spec with op |
| 12 | +/// codes. |
| 13 | +/// |
| 14 | +//===----------------------------------------------------------------------===// |
| 15 | + |
| 16 | +#ifndef SPIRV_LIBSPIRV_SPIRVASM_H |
| 17 | +#define SPIRV_LIBSPIRV_SPIRVASM_H |
| 18 | + |
| 19 | +#include "SPIRVEntry.h" |
| 20 | +#include "SPIRVInstruction.h" |
| 21 | +#include "SPIRVValue.h" |
| 22 | + |
| 23 | +namespace SPIRV { |
| 24 | + |
| 25 | +class SPIRVAsmTargetINTEL : public SPIRVEntry { |
| 26 | +public: |
| 27 | + static const SPIRVWord FixedWC = 2; |
| 28 | + static const Op OC = OpAsmTargetINTEL; |
| 29 | + // Complete constructor |
| 30 | + SPIRVAsmTargetINTEL(SPIRVModule *M, SPIRVId TheId, |
| 31 | + const std::string &TheTarget) |
| 32 | + : SPIRVEntry(M, FixedWC + getSizeInWords(TheTarget), OC, TheId), |
| 33 | + Target(TheTarget) { |
| 34 | + validate(); |
| 35 | + } |
| 36 | + // Incomplete constructor |
| 37 | + SPIRVAsmTargetINTEL() : SPIRVEntry(OC) {} |
| 38 | + SPIRVCapVec getRequiredCapability() const override { |
| 39 | + return getVec(CapabilityAsmINTEL); |
| 40 | + } |
| 41 | + SPIRVExtSet getRequiredExtensions() const override { |
| 42 | + return getSet(ExtensionID::SPV_INTEL_inline_assembly); |
| 43 | + } |
| 44 | + const std::string &getTarget() const { return Target; } |
| 45 | + |
| 46 | +protected: |
| 47 | + void validate() const override { |
| 48 | + SPIRVEntry::validate(); |
| 49 | + assert(WordCount > FixedWC); |
| 50 | + assert(OpCode == OC); |
| 51 | + } |
| 52 | + _SPIRV_DEF_ENCDEC2(Id, Target) |
| 53 | + std::string Target; |
| 54 | +}; |
| 55 | + |
| 56 | +class SPIRVAsmINTEL : public SPIRVValue { |
| 57 | +public: |
| 58 | + static const SPIRVWord FixedWC = 5; |
| 59 | + static const Op OC = OpAsmINTEL; |
| 60 | + // Complete constructor |
| 61 | + SPIRVAsmINTEL(SPIRVModule *M, SPIRVTypeFunction *TheFunctionType, |
| 62 | + SPIRVId TheId, SPIRVAsmTargetINTEL *TheTarget, |
| 63 | + const std::string &TheInstructions, |
| 64 | + const std::string &TheConstraints) |
| 65 | + : SPIRVValue(M, |
| 66 | + FixedWC + getSizeInWords(TheInstructions) + |
| 67 | + getSizeInWords(TheConstraints), |
| 68 | + OC, TheFunctionType->getReturnType(), TheId), |
| 69 | + Target(TheTarget), FunctionType(TheFunctionType), |
| 70 | + Instructions(TheInstructions), Constraints(TheConstraints) { |
| 71 | + validate(); |
| 72 | + } |
| 73 | + // Incomplete constructor |
| 74 | + SPIRVAsmINTEL() : SPIRVValue(OC) {} |
| 75 | + SPIRVCapVec getRequiredCapability() const override { |
| 76 | + return getVec(CapabilityAsmINTEL); |
| 77 | + } |
| 78 | + SPIRVExtSet getRequiredExtensions() const override { |
| 79 | + return getSet(ExtensionID::SPV_INTEL_inline_assembly); |
| 80 | + } |
| 81 | + const std::string &getInstructions() const { return Instructions; } |
| 82 | + const std::string &getConstraints() const { return Constraints; } |
| 83 | + SPIRVTypeFunction *getFunctionType() const { return FunctionType; } |
| 84 | + |
| 85 | +protected: |
| 86 | + _SPIRV_DEF_ENCDEC6(Type, Id, FunctionType, Target, Instructions, Constraints) |
| 87 | + void validate() const override { |
| 88 | + SPIRVValue::validate(); |
| 89 | + assert(WordCount > FixedWC); |
| 90 | + assert(OpCode == OC); |
| 91 | + } |
| 92 | + SPIRVAsmTargetINTEL *Target; |
| 93 | + SPIRVTypeFunction *FunctionType; |
| 94 | + std::string Instructions; |
| 95 | + std::string Constraints; |
| 96 | +}; |
| 97 | + |
| 98 | +class SPIRVAsmCallINTEL : public SPIRVInstruction { |
| 99 | +public: |
| 100 | + static const SPIRVWord FixedWC = 4; |
| 101 | + static const Op OC = OpAsmCallINTEL; |
| 102 | + // Complete constructor |
| 103 | + SPIRVAsmCallINTEL(SPIRVId TheId, SPIRVAsmINTEL *TheAsm, |
| 104 | + const std::vector<SPIRVWord> &TheArgs, |
| 105 | + SPIRVBasicBlock *TheBB) |
| 106 | + : SPIRVInstruction(FixedWC + TheArgs.size(), OC, TheAsm->getType(), TheId, |
| 107 | + TheBB), |
| 108 | + Asm(TheAsm), Args(TheArgs) { |
| 109 | + validate(); |
| 110 | + } |
| 111 | + // Incomplete constructor |
| 112 | + SPIRVAsmCallINTEL() : SPIRVInstruction(OC) {} |
| 113 | + SPIRVCapVec getRequiredCapability() const override { |
| 114 | + return getVec(CapabilityAsmINTEL); |
| 115 | + } |
| 116 | + SPIRVExtSet getRequiredExtensions() const override { |
| 117 | + return getSet(ExtensionID::SPV_INTEL_inline_assembly); |
| 118 | + } |
| 119 | + bool isOperandLiteral(unsigned int Index) const override { return false; } |
| 120 | + void setWordCount(SPIRVWord TheWordCount) override { |
| 121 | + SPIRVEntry::setWordCount(TheWordCount); |
| 122 | + Args.resize(TheWordCount - FixedWC); |
| 123 | + } |
| 124 | + const std::vector<SPIRVWord> &getArguments() const { return Args; } |
| 125 | + |
| 126 | + SPIRVAsmINTEL *getAsm() const { return Asm; } |
| 127 | + |
| 128 | +protected: |
| 129 | + _SPIRV_DEF_ENCDEC4(Type, Id, Asm, Args) |
| 130 | + void validate() const override { |
| 131 | + SPIRVInstruction::validate(); |
| 132 | + assert(WordCount >= FixedWC); |
| 133 | + assert(OpCode == OC); |
| 134 | + assert(getBasicBlock() && "Invalid BB"); |
| 135 | + assert(getBasicBlock()->getModule() == Asm->getModule()); |
| 136 | + } |
| 137 | + SPIRVAsmINTEL *Asm; |
| 138 | + std::vector<SPIRVWord> Args; |
| 139 | +}; |
| 140 | + |
| 141 | +} // namespace SPIRV |
| 142 | +#endif // SPIRV_LIBSPIRV_SPIRVASM_H |
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