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KorovinVladvmaksimo
KorovinVlad
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vmaksimo
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[Backport to 12] Support SPV_INTEL_maximum_registers extension (#2344) (#2400)
Co-authored-by: Viktoria Maximova <viktoria.maksimova@intel.com>
1 parent ccb8266 commit e6652c0

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15 files changed

+296
-54
lines changed

15 files changed

+296
-54
lines changed

‎.clang-tidy‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
Checks: '-*,clang-diagnostic-*,llvm-*,misc-*,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
2-
WarningsAsErrors: 'llvm-*,misc-*,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
1+
Checks: '-*,clang-diagnostic-*,llvm-*,misc-*,-misc-no-recursion,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
2+
WarningsAsErrors: 'llvm-*,misc-*,-misc-no-recursion,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
33
CheckOptions:
44
- key: readability-identifier-naming.ClassCase
55
value: CamelCase
@@ -17,4 +17,3 @@ CheckOptions:
1717
value: CamelCase
1818
- key: llvm-namespace-comment.ShortNamespaceLines
1919
value: '25'
20-

‎include/LLVMSPIRVExtensions.inc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,3 +47,4 @@ EXT(SPV_INTEL_tensor_float32_conversion) // TODO: to remove old extension
4747
EXT(SPV_INTEL_tensor_float32_rounding)
4848
EXT(SPV_INTEL_hw_thread_queries)
4949
EXT(SPV_EXT_relaxed_printf_string_address_space)
50+
EXT(SPV_INTEL_maximum_registers)

‎lib/SPIRV/SPIRVReader.cpp‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3599,6 +3599,48 @@ bool SPIRVToLLVM::transMetadata() {
35993599
F->setMetadata(kSPIR2MD::FmaxMhz,
36003600
getMDNodeStringIntVec(Context, EM->getLiterals()));
36013601
}
3602+
if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersINTEL)) {
3603+
NamedMDNode *ExecModeMD =
3604+
M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);
3605+
3606+
SmallVector<Metadata *, 4> ValueVec;
3607+
ValueVec.push_back(ConstantAsMetadata::get(F));
3608+
ValueVec.push_back(
3609+
ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
3610+
ValueVec.push_back(
3611+
ConstantAsMetadata::get(getUInt32(M, EM->getLiterals()[0])));
3612+
ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
3613+
}
3614+
if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersIdINTEL)) {
3615+
NamedMDNode *ExecModeMD =
3616+
M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);
3617+
3618+
SmallVector<Metadata *, 4> ValueVec;
3619+
ValueVec.push_back(ConstantAsMetadata::get(F));
3620+
ValueVec.push_back(
3621+
ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
3622+
3623+
auto *ExecOp = BF->getModule()->getValue(EM->getLiterals()[0]);
3624+
ValueVec.push_back(
3625+
MDNode::get(*Context, ConstantAsMetadata::get(cast<ConstantInt>(
3626+
transValue(ExecOp, nullptr, nullptr)))));
3627+
ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
3628+
}
3629+
if (auto *EM =
3630+
BF->getExecutionMode(ExecutionModeNamedMaximumRegistersINTEL)) {
3631+
NamedMDNode *ExecModeMD =
3632+
M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);
3633+
3634+
SmallVector<Metadata *, 4> ValueVec;
3635+
ValueVec.push_back(ConstantAsMetadata::get(F));
3636+
ValueVec.push_back(
3637+
ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
3638+
3639+
assert(EM->getLiterals()[0] == 0 &&
3640+
"Invalid named maximum number of registers");
3641+
ValueVec.push_back(MDString::get(*Context, "AutoINTEL"));
3642+
ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
3643+
}
36023644
}
36033645
NamedMDNode *MemoryModelMD =
36043646
M->getOrInsertNamedMetadata(kSPIRVMD::MemoryModel);

‎lib/SPIRV/SPIRVWriter.cpp‎

Lines changed: 63 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -671,6 +671,9 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) {
671671

672672
transFPGAFunctionMetadata(BF, F);
673673

674+
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_maximum_registers))
675+
transFunctionMetadataAsExecutionMode(BF, F);
676+
674677
SPIRVDBG(dbgs() << "[transFunction] " << *F << " => ";
675678
spvdbgs() << *BF << '\n';)
676679
return BF;
@@ -769,6 +772,38 @@ void LLVMToSPIRV::transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F) {
769772
}
770773
}
771774

775+
void LLVMToSPIRV::transFunctionMetadataAsExecutionMode(SPIRVFunction *BF,
776+
Function *F) {
777+
SmallVector<MDNode *, 1> RegisterAllocModeMDs;
778+
F->getMetadata("RegisterAllocMode", RegisterAllocModeMDs);
779+
780+
for (unsigned I = 0; I < RegisterAllocModeMDs.size(); I++) {
781+
auto *RegisterAllocMode = RegisterAllocModeMDs[I]->getOperand(0).get();
782+
if (isa<MDString>(RegisterAllocMode)) {
783+
const std::string Str = getMDOperandAsString(RegisterAllocModeMDs[I], 0);
784+
const NamedMaximumNumberOfRegisters NamedValue =
785+
SPIRVNamedMaximumNumberOfRegistersNameMap::rmap(Str);
786+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
787+
OpExecutionMode, BF, ExecutionModeNamedMaximumRegistersINTEL,
788+
NamedValue)));
789+
} else if (isa<MDNode>(RegisterAllocMode)) {
790+
auto *RegisterAllocNodeMDOp =
791+
getMDOperandAsMDNode(RegisterAllocModeMDs[I], 0);
792+
const int Num = getMDOperandAsInt(RegisterAllocNodeMDOp, 0);
793+
auto *Const =
794+
BM->addConstant(transType(Type::getInt32Ty(F->getContext())), Num);
795+
BF->addExecutionMode(BM->add(new SPIRVExecutionModeId(
796+
BF, ExecutionModeMaximumRegistersIdINTEL, Const->getId())));
797+
} else {
798+
const int64_t RegisterAllocVal =
799+
mdconst::dyn_extract<ConstantInt>(RegisterAllocMode)->getZExtValue();
800+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
801+
OpExecutionMode, BF, ExecutionModeMaximumRegistersINTEL,
802+
RegisterAllocVal)));
803+
}
804+
}
805+
}
806+
772807
SPIRVValue *LLVMToSPIRV::transConstant(Value *V) {
773808
if (auto CPNull = dyn_cast<ConstantPointerNull>(V))
774809
return BM->addNullConstant(
@@ -3681,14 +3716,14 @@ bool LLVMToSPIRV::transExecutionMode() {
36813716

36823717
switch (EMode) {
36833718
case spv::ExecutionModeContractionOff:
3684-
BF->addExecutionMode(BM->add(
3685-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
3719+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3720+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
36863721
break;
36873722
case spv::ExecutionModeInitializer:
36883723
case spv::ExecutionModeFinalizer:
36893724
if (BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_1)) {
3690-
BF->addExecutionMode(BM->add(
3691-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
3725+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3726+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
36923727
} else {
36933728
getErrorLog().checkError(false, SPIRVEC_Requires1_1,
36943729
"Initializer/Finalizer Execution Mode");
@@ -3700,33 +3735,34 @@ bool LLVMToSPIRV::transExecutionMode() {
37003735
unsigned X, Y, Z;
37013736
N.get(X).get(Y).get(Z);
37023737
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3703-
BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
3738+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
37043739
} break;
37053740
case spv::ExecutionModeMaxWorkgroupSizeINTEL: {
37063741
if (BM->isAllowedToUseExtension(
37073742
ExtensionID::SPV_INTEL_kernel_attributes)) {
37083743
unsigned X, Y, Z;
37093744
N.get(X).get(Y).get(Z);
37103745
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3711-
BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
3746+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X, Y,
3747+
Z)));
37123748
BM->addCapability(CapabilityKernelAttributesINTEL);
37133749
}
37143750
} break;
37153751
case spv::ExecutionModeNoGlobalOffsetINTEL: {
3716-
if (BM->isAllowedToUseExtension(
3717-
ExtensionID::SPV_INTEL_kernel_attributes)) {
3718-
BF->addExecutionMode(BM->add(
3719-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
3720-
BM->addCapability(CapabilityKernelAttributesINTEL);
3721-
}
3752+
if (!BM->isAllowedToUseExtension(
3753+
ExtensionID::SPV_INTEL_kernel_attributes))
3754+
break;
3755+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3756+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
3757+
BM->addCapability(CapabilityKernelAttributesINTEL);
37223758
} break;
37233759
case spv::ExecutionModeVecTypeHint:
37243760
case spv::ExecutionModeSubgroupSize:
37253761
case spv::ExecutionModeSubgroupsPerWorkgroup: {
37263762
unsigned X;
37273763
N.get(X);
3728-
BF->addExecutionMode(BM->add(
3729-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode), X)));
3764+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3765+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X)));
37303766
} break;
37313767
case spv::ExecutionModeNumSIMDWorkitemsINTEL:
37323768
case spv::ExecutionModeSchedulerTargetFmaxMhzINTEL:
@@ -3736,7 +3772,7 @@ bool LLVMToSPIRV::transExecutionMode() {
37363772
unsigned X;
37373773
N.get(X);
37383774
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3739-
BF, static_cast<ExecutionMode>(EMode), X)));
3775+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X)));
37403776
BM->addCapability(CapabilityFPGAKernelAttributesINTEL);
37413777
}
37423778
} break;
@@ -3746,15 +3782,16 @@ bool LLVMToSPIRV::transExecutionMode() {
37463782
unsigned SLMSize;
37473783
N.get(SLMSize);
37483784
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3749-
BF, static_cast<ExecutionMode>(EMode), SLMSize)));
3785+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), SLMSize)));
37503786
} break;
37513787
case spv::ExecutionModeNamedBarrierCountINTEL: {
37523788
if (!BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
37533789
break;
37543790
unsigned NBarrierCnt = 0;
37553791
N.get(NBarrierCnt);
3756-
BF->addExecutionMode(new SPIRVExecutionMode(
3757-
BF, static_cast<ExecutionMode>(EMode), NBarrierCnt));
3792+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3793+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode),
3794+
NBarrierCnt)));
37583795
BM->addExtension(ExtensionID::SPV_INTEL_vector_compute);
37593796
BM->addCapability(CapabilityVectorComputeINTEL);
37603797
} break;
@@ -3769,7 +3806,8 @@ bool LLVMToSPIRV::transExecutionMode() {
37693806
unsigned TargetWidth;
37703807
N.get(TargetWidth);
37713808
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3772-
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
3809+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode),
3810+
TargetWidth)));
37733811
} break;
37743812
case spv::ExecutionModeRoundingModeRTPINTEL:
37753813
case spv::ExecutionModeRoundingModeRTNINTEL:
@@ -3781,12 +3819,13 @@ bool LLVMToSPIRV::transExecutionMode() {
37813819
unsigned TargetWidth;
37823820
N.get(TargetWidth);
37833821
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3784-
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
3822+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode),
3823+
TargetWidth)));
37853824
} break;
37863825
case spv::ExecutionModeFastCompositeKernelINTEL: {
37873826
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite))
3788-
BF->addExecutionMode(BM->add(
3789-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
3827+
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
3828+
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
37903829
} break;
37913830
default:
37923831
llvm_unreachable("invalid execution mode");
@@ -3831,8 +3870,8 @@ void LLVMToSPIRV::transFPContract() {
38313870
}
38323871

38333872
if (DisableContraction) {
3834-
BF->addExecutionMode(BF->getModule()->add(
3835-
new SPIRVExecutionMode(BF, spv::ExecutionModeContractionOff)));
3873+
BF->addExecutionMode(BF->getModule()->add(new SPIRVExecutionMode(
3874+
OpExecutionMode, BF, spv::ExecutionModeContractionOff)));
38363875
}
38373876
}
38383877
}

‎lib/SPIRV/SPIRVWriter.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ class LLVMToSPIRV : public ModulePass {
118118
SPIRVFunction *transFunctionDecl(Function *F);
119119
void transVectorComputeMetadata(Function *F);
120120
void transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F);
121+
void transFunctionMetadataAsExecutionMode(SPIRVFunction *BF, Function *F);
121122
bool transGlobalVariables();
122123

123124
Op transBoolOpCode(SPIRVValue *Opn, Op OC);

‎lib/SPIRV/libSPIRV/SPIRVEntry.cpp‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -532,7 +532,7 @@ SPIRVEntryPoint::SPIRVEntryPoint(SPIRVModule *TheModule,
532532
SPIRVExecutionModelKind TheExecModel,
533533
SPIRVId TheId, const std::string &TheName,
534534
std::vector<SPIRVId> Variables)
535-
: SPIRVAnnotation(TheModule->get<SPIRVFunction>(TheId),
535+
: SPIRVAnnotation(OpEntryPoint, TheModule->get<SPIRVFunction>(TheId),
536536
getSizeInWords(TheName) + Variables.size() + 3),
537537
ExecModel(TheExecModel), Name(TheName), Variables(Variables) {}
538538

@@ -552,7 +552,7 @@ void SPIRVExecutionMode::encode(spv_ostream &O) const {
552552

553553
void SPIRVExecutionMode::decode(std::istream &I) {
554554
getDecoder(I) >> Target >> ExecMode;
555-
switch (ExecMode) {
555+
switch (static_cast<uint32_t>(ExecMode)) {
556556
case ExecutionModeLocalSize:
557557
case ExecutionModeLocalSizeHint:
558558
case ExecutionModeMaxWorkgroupSizeINTEL:
@@ -576,6 +576,9 @@ void SPIRVExecutionMode::decode(std::istream &I) {
576576
case ExecutionModeMaxWorkDimINTEL:
577577
case ExecutionModeNumSIMDWorkitemsINTEL:
578578
case ExecutionModeSchedulerTargetFmaxMhzINTEL:
579+
case ExecutionModeMaximumRegistersINTEL:
580+
case ExecutionModeMaximumRegistersIdINTEL:
581+
case ExecutionModeNamedMaximumRegistersINTEL:
579582
WordLiterals.resize(1);
580583
break;
581584
default:
@@ -597,7 +600,8 @@ SPIRVForward *SPIRVAnnotationGeneric::getOrCreateTarget() const {
597600
}
598601

599602
SPIRVName::SPIRVName(const SPIRVEntry *TheTarget, const std::string &TheStr)
600-
: SPIRVAnnotation(TheTarget, getSizeInWords(TheStr) + 2), Str(TheStr) {}
603+
: SPIRVAnnotation(OpName, TheTarget, getSizeInWords(TheStr) + 2),
604+
Str(TheStr) {}
601605

602606
void SPIRVName::encode(spv_ostream &O) const { getEncoder(O) << Target << Str; }
603607

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