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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Pete Johanson |
| 3 | + * Copyright (c) 2025 Silicon Laboratories Inc. |
| 4 | + * |
| 5 | + * SPDX-License-Identifier: Apache-2.0 |
| 6 | + */ |
| 7 | + |
| 8 | +/dts-v1/; |
| 9 | +#include <silabs/xg24/mgm240sd22vna.dtsi> |
| 10 | +#include <zephyr/dt-bindings/input/input-event-codes.h> |
| 11 | +#include "arduino_nano_matter-pinctrl.dtsi" |
| 12 | +#include "arduino_nano_matter_connector.dtsi" |
| 13 | + |
| 14 | +/ { |
| 15 | + model = "Arduino Nano Matter"; |
| 16 | + compatible = "arduino,arduino_nano_matter", "silabs,mgm240sd22vna"; |
| 17 | + |
| 18 | + chosen { |
| 19 | + zephyr,bt-hci = &bt_hci_silabs; |
| 20 | + zephyr,code-partition = &slot0_partition; |
| 21 | + zephyr,console = &usart0; |
| 22 | + zephyr,flash = &flash0; |
| 23 | + zephyr,shell-uart = &usart0; |
| 24 | + zephyr,sram = &sram0; |
| 25 | + zephyr,uart-pipe = &usart0; |
| 26 | + }; |
| 27 | + |
| 28 | + /* These aliases are provided for compatibility with samples */ |
| 29 | + aliases { |
| 30 | + led0 = &led0; |
| 31 | + led1 = &led1; |
| 32 | + led2 = &led2; |
| 33 | + sw0 = &button0; |
| 34 | + watchdog0 = &wdog0; |
| 35 | + }; |
| 36 | + |
| 37 | + leds { |
| 38 | + compatible = "gpio-leds"; |
| 39 | + |
| 40 | + led0: led_0 { |
| 41 | + gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; |
| 42 | + label = "LED 0"; |
| 43 | + }; |
| 44 | + |
| 45 | + led1: led_1 { |
| 46 | + gpios = <&gpioc 2 GPIO_ACTIVE_LOW>; |
| 47 | + label = "LED 1"; |
| 48 | + }; |
| 49 | + |
| 50 | + led2: led_2 { |
| 51 | + gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; |
| 52 | + label = "LED 2"; |
| 53 | + }; |
| 54 | + }; |
| 55 | + |
| 56 | + buttons { |
| 57 | + compatible = "gpio-keys"; |
| 58 | + |
| 59 | + button0: button_0 { |
| 60 | + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; |
| 61 | + zephyr,code = <INPUT_KEY_0>; |
| 62 | + }; |
| 63 | + }; |
| 64 | +}; |
| 65 | + |
| 66 | +&cpu0 { |
| 67 | + clock-frequency = <78000000>; |
| 68 | +}; |
| 69 | + |
| 70 | +&pstate_em3 { |
| 71 | + status = "disabled"; |
| 72 | +}; |
| 73 | + |
| 74 | +&hfxo { |
| 75 | + ctune = <95>; |
| 76 | + precision = <50>; |
| 77 | + status = "okay"; |
| 78 | +}; |
| 79 | + |
| 80 | +&lfxo { |
| 81 | + ctune = <44>; |
| 82 | + precision = <50>; |
| 83 | + status = "okay"; |
| 84 | +}; |
| 85 | + |
| 86 | +&hfrcodpll { |
| 87 | + clock-frequency = <DT_FREQ_M(78)>; |
| 88 | + clocks = <&hfxo>; |
| 89 | + dpll-autorecover; |
| 90 | + dpll-edge = "fall"; |
| 91 | + dpll-lock = "phase"; |
| 92 | + dpll-m = <1919>; |
| 93 | + dpll-n = <3839>; |
| 94 | +}; |
| 95 | + |
| 96 | +&em23grpaclk { |
| 97 | + clocks = <&lfxo>; |
| 98 | +}; |
| 99 | + |
| 100 | +&em4grpaclk { |
| 101 | + clocks = <&lfxo>; |
| 102 | +}; |
| 103 | + |
| 104 | +&sysrtcclk { |
| 105 | + clocks = <&lfxo>; |
| 106 | +}; |
| 107 | + |
| 108 | +&wdog0clk { |
| 109 | + clocks = <&lfxo>; |
| 110 | +}; |
| 111 | + |
| 112 | +&wdog1clk { |
| 113 | + clocks = <&lfxo>; |
| 114 | +}; |
| 115 | + |
| 116 | +&usart0 { |
| 117 | + current-speed = <115200>; |
| 118 | + pinctrl-0 = <&usart0_default>; |
| 119 | + pinctrl-names = "default"; |
| 120 | + status = "okay"; |
| 121 | +}; |
| 122 | + |
| 123 | +&eusart0 { |
| 124 | + compatible = "silabs,eusart-uart"; |
| 125 | + current-speed = <115200>; |
| 126 | + pinctrl-0 = <&eusart0_default>; |
| 127 | + pinctrl-names = "default"; |
| 128 | +}; |
| 129 | + |
| 130 | +&eusart1 { |
| 131 | + compatible = "silabs,eusart-spi"; |
| 132 | + #address-cells = <1>; |
| 133 | + #size-cells = <0>; |
| 134 | + clock-frequency = <4000000>; |
| 135 | + cs-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; |
| 136 | + pinctrl-0 = <&eusart1_default>; |
| 137 | + pinctrl-names = "default"; |
| 138 | +}; |
| 139 | + |
| 140 | +&i2c0 { |
| 141 | + pinctrl-0 = <&i2c0_default>; |
| 142 | + pinctrl-names = "default"; |
| 143 | +}; |
| 144 | + |
| 145 | +&gpio { |
| 146 | + location-swo = <0>; |
| 147 | + status = "okay"; |
| 148 | +}; |
| 149 | + |
| 150 | +&gpioa { |
| 151 | + status = "okay"; |
| 152 | +}; |
| 153 | + |
| 154 | +&gpiob { |
| 155 | + status = "okay"; |
| 156 | +}; |
| 157 | + |
| 158 | +&gpioc { |
| 159 | + status = "okay"; |
| 160 | +}; |
| 161 | + |
| 162 | +&gpiod { |
| 163 | + status = "okay"; |
| 164 | +}; |
| 165 | + |
| 166 | +&wdog0 { |
| 167 | + status = "okay"; |
| 168 | +}; |
| 169 | + |
| 170 | +&sysrtc0 { |
| 171 | + status = "okay"; |
| 172 | +}; |
| 173 | + |
| 174 | +&se { |
| 175 | + status = "okay"; |
| 176 | +}; |
| 177 | + |
| 178 | +&flash0 { |
| 179 | + partitions { |
| 180 | + compatible = "fixed-partitions"; |
| 181 | + #address-cells = <1>; |
| 182 | + #size-cells = <1>; |
| 183 | + |
| 184 | + /* Reserve 48 kB for the bootloader */ |
| 185 | + boot_partition: partition@0 { |
| 186 | + reg = <0x0 DT_SIZE_K(48)>; |
| 187 | + label = "mcuboot"; |
| 188 | + read-only; |
| 189 | + }; |
| 190 | + |
| 191 | + /* Reserve 736 kB for the application in slot 0 */ |
| 192 | + slot0_partition: partition@c000 { |
| 193 | + reg = <0x0000c000 0x000B8000>; |
| 194 | + label = "image-0"; |
| 195 | + }; |
| 196 | + |
| 197 | + /* Reserve 736 kB for the application in slot 1 */ |
| 198 | + slot1_partition: partition@C4000 { |
| 199 | + reg = <0x000C4000 0x000B8000>; |
| 200 | + label = "image-1"; |
| 201 | + }; |
| 202 | + |
| 203 | + /* Set 16 kB of storage at the end of the 1536 kB of flash */ |
| 204 | + storage_partition: partition@17c000 { |
| 205 | + reg = <0x0017c000 DT_SIZE_K(16)>; |
| 206 | + label = "storage"; |
| 207 | + }; |
| 208 | + }; |
| 209 | +}; |
| 210 | + |
| 211 | +&bt_hci_silabs { |
| 212 | + status = "okay"; |
| 213 | +}; |
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