[AMDGPU][MC] Correct definition of aliases

Differential Revision: https://reviews.llvm.org/D136370

Author: dpreobra

llvm/lib/Target/AMDGPU/VOP2Instructions.td

@@ -269,7 +269,8 @@ class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
                       string OpName, string opnd> :
   InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
              (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
-                   ps.Pfl.Src1RC32:$src1)>,
+                   ps.Pfl.Src1RC32:$src1),
+             1, inst.AsmVariantName>,
   PredicateControl {
 }
 
@@ -331,12 +332,15 @@ multiclass
 class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
   InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
              (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
-                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
+                   ps.Pfl.Src1RC32:$src1),
+             1, inst.AsmVariantName>,
+  PredicateControl;
 
 class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
   InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
              (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
-                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
+                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp),
+             1, inst.AsmVariantName>,
   PredicateControl;
 
 multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {

llvm/lib/Target/AMDGPU/VOPCInstructions.td

@@ -1404,14 +1404,14 @@ let AssemblerPredicate = isGFX11Only in {
         VOPCe<op{7-0}>,
         MnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic,
                           pseudo_mnemonic),
-                      asm_name>,
+                      asm_name, ps32.AsmVariantName>,
         Requires<[isGFX11Plus]>;
       def _e64_gfx11 :
             VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
             VOP3a_gfx11<{0, op}, ps64.Pfl>,
             MnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic,
                               pseudo_mnemonic),
-                          asm_name>,
+                          asm_name, ps64.AsmVariantName>,
             Requires<[isGFX11Plus]> {
         // Encoding used for VOPC instructions encoded as VOP3 differs from
         // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
@@ -1568,7 +1568,7 @@ let AssemblerPredicate = isGFX11Only in {
           : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
             MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic),
                               pseudo_mnemonic),
-                          asm_name>,
+                          asm_name, ps32.AsmVariantName>,
             Requires<[isGFX11Plus]>,
             VOPCe<op{7-0}> {
         let AsmString = asm_name # "{_e32} " # ps32.AsmOperands;
@@ -1577,7 +1577,7 @@ let AssemblerPredicate = isGFX11Only in {
           : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
             MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic),
                               pseudo_mnemonic),
-                          asm_name>,
+                          asm_name, ps64.AsmVariantName>,
             Requires<[isGFX11Plus]>,
             VOP3a_gfx11<{0, op}, ps64.Pfl> {
         let Inst{7-0} = ? ; // sdst

llvm/test/MC/AMDGPU/gfx10_asm_vop2.s

@@ -101,7 +101,7 @@ v_cndmask_b32_e64 v5, v1, v2, s[100:101]
 
 v_cndmask_b32_e64 v5, v1, v2, vcc
 // W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cndmask_b32_e64 v5, -v1, |v2|, vcc
 // W64: encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
@@ -229,7 +229,7 @@ v_cndmask_b32_e64 v5, v1, v2, s100
 
 v_cndmask_b32_e64 v5, v1, v2, vcc_lo
 // W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cndmask_b32_e64 v5, -v1, |v2|, vcc_lo
 // W32: encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]