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Arseny Bochkarev edited this page Apr 13, 2025 · 39 revisions

13-apr-25:

  • We need to add meeting with Syntacore to our calendar

06-apr-25:

  • ITMO sprint took place:
    • The picture from the Syntacore presentation should be added to the one for ITMO
    • The Exegesis tasks should be clarified a bit IMO (what is the open-source patch exactly?)
  • MCA:
    • The proposal for SchedModel widening was written. The main idea was to add additional resources for vector instructions' MOPs. For the feedback see below.
    • The MCA doesn't go to TableGen at all. The codegen feeds it with the MCInsts. So basically the proposal in its current state is not applicable.
    • The MCA is able to replace one instruction with the other: once it gets MCInst from codegen, it creates MCAInst based on it. For RVV it creates proper version of instruction, based on the LMUL
    • Current plan is the following:
      • To understand how the instructions are chosen
      • To teach MCA to create multiple MCAInsts based on LMUL
      • To support it inside SchedModel (fix numbers in subtargets a bit)
  • Exegesis:
    • Sergey and Dmitry Sokolov started to apply the patch to our current main

30-mar-25:

  • MCA:
    • MCA mostly interacts with common LLVM classes, not TableGen directly
    • The only suitable exception is RISCVCustomBehaviour, it should be possible to extract there (see the opcodeHasEEWAndEMULInfo as an example)
    • SchedModel widening: added custom class for MOP resources occupied by every vector instruction. The subtargets can then define them accordingly
  • Exegesis:
    • Sergey and Dmitry Sokolov will take the patch and try to apply it to current main branch
    • Dmitry Zubakhin will investigate current snippets generation for different instructions

28-mar-25 (ITMO):

  • Transferred context to ITMO curator
  • We should think about doing one project at a time (Exegesis or MCA), not two tools simultaneously

26-mar-25 (Syntacore):

  • The working plan and decomposition for LLVM-Exegesis is fine
  • The job which should be done for MCA tool is not the one we thought:
    • We need to emulate MOPs as they are in Kanata:

One instruction corresponds to LMUL MOPs, who essentially are just LMUL completely similar instructions one-by-one

  • The interactions with the Green team are close...

23-mar-25 (MCA):

  • Some info on Sched Models: https://github.com/LLVM-Exegesis-MCA-RVV/llvm-project/issues/2
  • Denis is looking for the whole MCA single instruction pipeline
    • Looks like TableGen-generated code can call some C++ code? Curious
  • Next steps are:
    • Try to understand how uOps can help us with vector instructions in particular (ask Anton)
    • Understand how a single instruction is processed
    • Next, try to connect our approach with resource division on pipeline stages with some simple instruction

22-mar-25 (Exegesis):

  • Article about RVV: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nutshell-part-1
  • Patch from SiFive:
    • Problem is: same instructions produce different results based on vsetvl
    • Current solution is:
      • Generate all possible vector unit programming cases in snippets for benchmarking using multiple passes:
        • RISCVInsertVSETVIPass
        • RISCVInsertWriteVXRMPass
        • Post-processing pass
      • Patch introduced opcodes in MCInstr
  • Dmitry Zubakhin will check some "unsupported" instructions
  • Arseny will reach out to one of Winter School curators to ask what was done

16-mar-25 (Exegesis):

16-mar-25 (MCA):

  • Read: https://habr.com/ru/articles/474460/
  • grep how MCA uses SchedModel (I guess we should not change any interfaces)
  • scalable vectorization in other CPUs in LLVM: What's number of microops?
  • take a look at MCA for SiFive CPUs
  • Need to add FU count in a sched model
  • RISCVSchedSiFiveP400.td for reference
    • Try to feed to MCA, how it handles RVV

12-mar-25 (Syntacore):

  • More interactions with green team
  • performance tools (llvm-based):
    • llvm-mca: code analysis (any random code snippet)
    • llvm-exegesis: hardware analysis
  • We need to try to union them in some sort
  • Exegesis doesn't use LLVM's SchedModel as full as possible. Initial RVV is supported
  • Traditional LLVM's SchedModel doesn't suite RVV well: we need to widen it (e.g. functional units number)
  • MCA RVV: no rvv at all
  • Decomp: mca rvv , schedmodel for exegesis , widening schedmodel for RVV, bring-up (saturn-vectors, real hardware)
  • Need to do decomposition
  • Org
    • Biweekly meetings
    • Monthly -- both teams
    • Next meeting: 19-mar-25
  • Need to get familiar with both tools
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