Document pinout voltage levels

[g-v-egidy]

Thank you very much for adding the documentation about the pinouts.

It would be nice if you could also add a column in the pinout table of the SODIMM pinout that documents the voltage level of each pin.

For example UART0_RXD and UART0_TXD - are they 3.3V CMOS or 1.8V? The same for SLS_S0 / SLS_S3, the GPIO, the SPI, the I2C buses.

The schematics for the Full EVA Carrier has a note that some voltage levels can be changed. If I understood this correctly, this is probably done together for several IOs that are on one voltage rail. Then please document which pins are together on one voltage rail and what is the default voltage level.

Regarding the TSENSE pin: this is probably a NTC that has 10 kOhms at 25°C. Could you please document which beta value to use for proper temperature readout?

[alphaarea]

All low-speed interfaces are at 3.3V level, including UART, I2C, GPIO, etc. I'm working on a detailed pinout document.

All pins from the SoC can be configured to 3.3V or 1.8V in the BIOS source code. But 1.8V has negligible power savings compared to 3.3V, and is much more cumbersome to use than 3.3V. So all the pins are configured to 3.3V.

The TSENSE pin is adapted to the 10K B3950 NTC. This will be improved in the detailed pinout document.

[g-v-egidy]

Thank you very much for the explanation. I'm looking forward to seeing your detailed pinout document.