Slow clock on Tang Primer board

[andrsmllr]

What is the reason for slowclk running at only 32.786 kHz (8.388 MHz divided by 256) on the Tang Primer board? Especially since slowclk is driving almost all the logic in the design.
I changed the top level Verilog file and e203egmini_new.sdc constraint file so slowclk is the same as clk_8388 and it seems to build just fine, no timing errors.
It would be of great interest why the system clock was chosen to be so slow, since this is very uncommon.

[xelll]

slowclkis only for rtc use

[andrsmllr]

Yes slowclk probably should only be used for RTC applications. However, this is not how slowclk is used in the "example project". This repository (a1f1d36) delivers a project file ./project/e203egmini_new.al where slowclk is used to drive the entire design.
Without digging through all the wrapper files this can be seen from the timing report.

To reproduce, check out the repository, open the project with TD and run implementation. The timing report should match what is shown in the screenshot above.

As mentioned before, the design will build fine with higher clock frequencies. The issue is that slowclk does drive most parts of the logic of the example design. This is certainly not how it is supposed to be.