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Commit b71f767

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Applied SX1272 and SX1276 radios errata note 3.1 to the radio drivers implementation.
1 parent d85aedd commit b71f767

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2 files changed

+20
-7
lines changed

2 files changed

+20
-7
lines changed

src/radio/sx1272/sx1272.c

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1457,11 +1457,17 @@ void SX1272OnDio1Irq( void* context )
14571457
SX1272.Settings.FskPacketHandler.Size = SX1272Read( REG_PAYLOADLENGTH );
14581458
}
14591459
}
1460-
1461-
if( ( SX1272.Settings.FskPacketHandler.Size - SX1272.Settings.FskPacketHandler.NbBytes ) > SX1272.Settings.FskPacketHandler.FifoThresh )
1460+
// ERRATA 3.1 - PayloadReady Set for 31.25ns if FIFO is Empty
1461+
//
1462+
// When FifoLevel interrupt is used to offload the
1463+
// FIFO, the microcontroller should monitor both
1464+
// PayloadReady and FifoLevel interrupts, and
1465+
// read only (FifoThreshold-1) bytes off the FIFO
1466+
// when FifoLevel fires
1467+
if( ( SX1272.Settings.FskPacketHandler.Size - SX1272.Settings.FskPacketHandler.NbBytes ) >= SX1272.Settings.FskPacketHandler.FifoThresh )
14621468
{
1463-
SX1272ReadFifo( ( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes ), SX1272.Settings.FskPacketHandler.FifoThresh );
1464-
SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.FifoThresh;
1469+
SX1272ReadFifo( ( RxTxBuffer + SX1272.Settings.FskPacketHandler.NbBytes ), SX1272.Settings.FskPacketHandler.FifoThresh - 1 );
1470+
SX1272.Settings.FskPacketHandler.NbBytes += SX1272.Settings.FskPacketHandler.FifoThresh - 1;
14651471
}
14661472
else
14671473
{

src/radio/sx1276/sx1276.c

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1637,10 +1637,17 @@ void SX1276OnDio1Irq( void* context )
16371637
}
16381638
}
16391639

1640-
if( ( SX1276.Settings.FskPacketHandler.Size - SX1276.Settings.FskPacketHandler.NbBytes ) > SX1276.Settings.FskPacketHandler.FifoThresh )
1640+
// ERRATA 3.1 - PayloadReady Set for 31.25ns if FIFO is Empty
1641+
//
1642+
// When FifoLevel interrupt is used to offload the
1643+
// FIFO, the microcontroller should monitor both
1644+
// PayloadReady and FifoLevel interrupts, and
1645+
// read only (FifoThreshold-1) bytes off the FIFO
1646+
// when FifoLevel fires
1647+
if( ( SX1276.Settings.FskPacketHandler.Size - SX1276.Settings.FskPacketHandler.NbBytes ) >= SX1276.Settings.FskPacketHandler.FifoThresh )
16411648
{
1642-
SX1276ReadFifo( ( RxTxBuffer + SX1276.Settings.FskPacketHandler.NbBytes ), SX1276.Settings.FskPacketHandler.FifoThresh );
1643-
SX1276.Settings.FskPacketHandler.NbBytes += SX1276.Settings.FskPacketHandler.FifoThresh;
1649+
SX1276ReadFifo( ( RxTxBuffer + SX1276.Settings.FskPacketHandler.NbBytes ), SX1276.Settings.FskPacketHandler.FifoThresh - 1 );
1650+
SX1276.Settings.FskPacketHandler.NbBytes += SX1276.Settings.FskPacketHandler.FifoThresh - 1;
16441651
}
16451652
else
16461653
{

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