Added SX126x missing registers definitions

Author: mluis1

src/radio/sx126x/radio.c

@@ -735,13 +735,11 @@ void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth,
             // WORKAROUND - Optimizing the Inverted IQ Operation, see DS_SX1261-2_V1.2 datasheet chapter 15.4
             if( SX126x.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED )
             {
-                // RegIqPolaritySetup = @address 0x0736
-                SX126xWriteRegister( 0x0736, SX126xReadRegister( 0x0736 ) & ~( 1 << 2 ) );
+                SX126xWriteRegister( REG_IQ_POLARITY, SX126xReadRegister( REG_IQ_POLARITY ) & ~( 1 << 2 ) );
             }
             else
             {
-                // RegIqPolaritySetup @address 0x0736
-                SX126xWriteRegister( 0x0736, SX126xReadRegister( 0x0736 ) | ( 1 << 2 ) );
+                SX126xWriteRegister( REG_IQ_POLARITY, SX126xReadRegister( REG_IQ_POLARITY ) | ( 1 << 2 ) );
             }
             // WORKAROUND END
 
@@ -844,13 +842,11 @@ void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
     // WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see DS_SX1261-2_V1.2 datasheet chapter 15.1
     if( ( modem == MODEM_LORA ) && ( SX126x.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) )
     {
-        // RegTxModulation = @address 0x0889
-        SX126xWriteRegister( 0x0889, SX126xReadRegister( 0x0889 ) & ~( 1 << 2 ) );
+        SX126xWriteRegister( REG_TX_MODULATION, SX126xReadRegister( REG_TX_MODULATION ) & ~( 1 << 2 ) );
     }
     else
     {
-        // RegTxModulation = @address 0x0889
-        SX126xWriteRegister( 0x0889, SX126xReadRegister( 0x0889 ) | ( 1 << 2 ) );
+        SX126xWriteRegister( REG_TX_MODULATION, SX126xReadRegister( REG_TX_MODULATION ) | ( 1 << 2 ) );
     }
     // WORKAROUND END
 
@@ -1260,10 +1256,8 @@ void RadioIrqProcess( void )
                     SX126xSetOperatingMode( MODE_STDBY_RC );
 
                     // WORKAROUND - Implicit Header Mode Timeout Behavior, see DS_SX1261-2_V1.2 datasheet chapter 15.3
-                    // RegRtcControl = @address 0x0902
-                    SX126xWriteRegister( 0x0902, 0x00 );
-                    // RegEventMask = @address 0x0944
-                    SX126xWriteRegister( 0x0944, SX126xReadRegister( 0x0944 ) | ( 1 << 1 ) );
+                    SX126xWriteRegister( REG_RTC_CTRL, 0x00 );
+                    SX126xWriteRegister( REG_EVT_CLR, SX126xReadRegister( REG_EVT_CLR ) | ( 1 << 1 ) );
                     // WORKAROUND END
                 }
                 SX126xGetPayload( RadioRxPayload, &size , 255 );

src/radio/sx126x/sx126x.c

@@ -305,6 +305,8 @@ void SX126xSetRx( uint32_t timeout )
 
     SX126xSetOperatingMode( MODE_RX );
 
+    SX126xWriteRegister( REG_RX_GAIN, 0x94 ); // default gain
+
     buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
     buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
     buf[2] = ( uint8_t )( timeout & 0xFF );
@@ -317,7 +319,7 @@ void SX126xSetRxBoosted( uint32_t timeout )
 
     SX126xSetOperatingMode( MODE_RX );
 
-    SX126xWriteRegister( REG_RX_GAIN, 0x96 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensivity
+    SX126xWriteRegister( REG_RX_GAIN, 0x96 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity
 
     buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
     buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
@@ -549,8 +551,7 @@ void SX126xSetTxParams( int8_t power, RadioRampTimes_t rampTime )
     else // sx1262
     {
         // WORKAROUND - Better Resistance of the SX1262 Tx to Antenna Mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2
-        // RegTxClampConfig = @address 0x08D8
-        SX126xWriteRegister( 0x08D8, SX126xReadRegister( 0x08D8 ) | ( 0x0F << 1 ) );
+        SX126xWriteRegister( REG_TX_CLAMP_CFG, SX126xReadRegister( REG_TX_CLAMP_CFG ) | ( 0x0F << 1 ) );
         // WORKAROUND END
 
         SX126xSetPaConfig( 0x04, 0x07, 0x00, 0x01 );

src/radio/sx126x/sx126x.h

@@ -151,6 +151,41 @@ extern "C"
  */
 #define REG_OCP                                     0x08E7
 
+/*!
+ * \brief Maximum number of register that can be added to the retention list
+ */
+#define MAX_NB_REG_IN_RETENTION                     4
+
+/*!
+ * \brief Base address of the register retention list
+ */
+#define REG_RETENTION_LIST_BASE_ADDRESS             0x029F
+
+/*!
+ * \brief WORKAROUND - Optimizing the Inverted IQ Operation, see DS_SX1261-2_V1.2 datasheet chapter 15.4
+ */
+#define REG_IQ_POLARITY                             0x0736
+
+/*!
+ * \brief WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see DS_SX1261-2_V1.2 datasheet chapter 15.1
+ */
+#define REG_TX_MODULATION                           0x0889
+
+/*!
+ * \brief WORKAROUND - Better resistance to antenna mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2
+ */
+#define REG_TX_CLAMP_CFG                            0x08D8
+
+/*!
+ * \brief RTC control
+ */
+#define REG_RTC_CTRL                                0x0902
+
+/*!
+ * \brief Event clear
+ */
+#define REG_EVT_CLR                                 0x0944
+
 /*!
  * \brief Structure describing the radio status
  */