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fix: Missing xiao_nrf54l15 board files are added
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‎boards/seeed/xiao_nrf54l15/Kconfig.defconfig‎

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# Copyright (c) 2024 Seeed Technology Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_XIAO_NRF54L15_NRF54L15_CPUAPP
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config BT_CTLR
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default BT
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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endif # BOARD_XIAO_NRF54L15_NRF54L15_CPUAPP

‎boards/seeed/xiao_nrf54l15/Kconfig.xiao_nrf54l15‎

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# Copyright (c) 2024 Seeed Technology Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_XIAO_NRF54L15
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select SOC_NRF54L15_CPUAPP if BOARD_XIAO_NRF54L15_NRF54L15_CPUAPP
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select SOC_NRF54L15_CPUFLPR if \
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BOARD_XIAO_NRF54L15_NRF54L15_CPUFLPR || \
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BOARD_XIAO_NRF54L15_NRF54L15_CPUFLPR_XIP

‎boards/seeed/xiao_nrf54l15/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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# Default Runner
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set(BOARD_FLASH_RUNNER pyocd)
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set(BOARD_DEBUG_RUNNER pyocd)
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# PYOCD
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board_runner_args(pyocd "--target=nrf54l")
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# JLINK
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if(CONFIG_SOC_NRF54L15_CPUAPP)
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board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
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elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
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board_runner_args(jlink "--device=nRF54L15_RV32")
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endif()
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

‎boards/seeed/xiao_nrf54l15/board.yml‎

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board:
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name: xiao_nrf54l15
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vendor: seeed
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socs:
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- name: nrf54l15
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variants:
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- name: xip
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cpucluster: cpuflpr

‎boards/seeed/xiao_nrf54l15/doc/index.rst‎

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.. zephyr:board:: xiao_nrf54l15
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Overview
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********
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Seeed Studio XIAO nRF54L15 is a compact, high-performance development board featuring the cutting-edge
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Nordic nRF54L15 chip. This next-generation SoC integrates an ultra-low power multiprotocol 2.4 GHz
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radio and an MCU with a 128 MHz Arm® Cortex®-M33 processor and an Arm® Cortex®-M0+ for advanced
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power management. It offers scalable memory up to 1.5 MB NVM and 256 KB RAM.
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Designed for exceptional ultra-low power consumption, it significantly extends battery life.
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Its robust radio supports Bluetooth® 6.0 (including Channel Sounding), Matter, Thread, Zigbee,
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and a high-throughput 2.4 GHz proprietary mode (up to 4 Mbps). The board includes a comprehensive
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set of peripherals, an integrated 128 MHz RISC-V coprocessor, and advanced security features like
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TrustZone® isolation and cryptographic engine protection. With built-in lithium battery management,
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XIAO nRF54L15 is ideal for compact, secure, and energy-efficient IoT solutions such as smart wearables,
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industrial sensors, and advanced human-machine interfaces.
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Hardware
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********
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- 128 MHz Arm® Cortex®-M33 processor
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- Scalable memory configurations up to 1.5 MB NVM and up to 256 KB RAM
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- Multiprotocol 2.4 GHz radio supporting Bluetooth Low Energy, 802.15.4-2020,
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and 2.4 GHz proprietary modes (up to 4 Mbps)
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- Comprehensive set of peripherals including new Global RTC available in System OFF,
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14-bit ADC, and high-speed serial interfaces
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- 128 MHz RISC-V coprocessor
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- Advanced security including TrustZone® isolation, tamper detection,
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and cryptographic engine side-channel leakage protection
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- Ultra-compact WLCSP (2.4x2.2 mm) and QFN (6.0x6.0 mm) packages
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For more information about the nRF54L15 SoC and XIAO nRF54L15 board, refer to these
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documents:
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- `nRF54L15 Website`_
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- `nRF54L15 Datasheet`_
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- `XIAO nRF54L15 Wiki`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Connections and IOs
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===================
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In the following table, the column **Name** contains Pin names. For example, P2_0
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means Pin number 0 on PORT2, as used in the board's datasheets and manuals.
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+-------+-------------+------------------+
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| Name | Function | Usage |
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+=======+=============+==================+
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| P2_0 | GPIO | LED0 |
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+-------+-------------+------------------+
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| P1_9 | USART20_TX | UART Console TX |
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+-------+-------------+------------------+
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| P1_8 | USART20_RX | UART Console RX |
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+-------+-------------+------------------+
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Programming and Debugging
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*************************
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The XIAO nRF54L15 contains an SAMD11 with CMSIS-DAP, allowing flashing, debugging, logging, etc. over
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the USB port. Doing so requires a version of OpenOCD that includes support for the flash on the nRF54L15
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MCU. Until those changes are included in stock OpenOCD, the version bundled with Arduino can be
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used, or can be installed from the `OpenOCD Arduino Fork`_. When flashing, debugging, etc. you may
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need to include ``--openocd=/usr/local/bin/openocd
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--openocd-search=/usr/local/share/openocd/scripts/`` options to the command.
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Flashing
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========
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Connect the XIAO nRF54L15 board to your host computer using the USB port. A USB CDC ACM serial port
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should appear on the host, that can be used to view logs from the flashed application.
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: xiao_nrf54l15
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:goals: flash
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Open a serial terminal (minicom, putty, etc.) connecting to the UCB CDC ACM serial port.
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Reset the board and you should see the following message in the terminal:
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.. code-block:: console
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Hello World! xiao_nrf54l15
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.. _XIAO nRF54L15 Wiki:
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https://wiki.seeedstudio.com/getting_started_with_xiao_nrf54l15/
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.. _nRF54L15 Website:
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https://www.nordicsemi.com/Products/nRF54L15
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.. _nRF54L15 Datasheet:
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https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/keyfeatures_html5.html
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.. _OpenOCD Arduino Fork:
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https://github.com/facchinm/OpenOCD/tree/arduino-0.12.0-rtx5

‎boards/seeed/xiao_nrf54l15/doc/xiao_nrf54l15.webp‎

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‎boards/seeed/xiao_nrf54l15/pre_dt_board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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# Suppress "unique_unit_address_if_enabled" to handle some overlaps
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list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")

‎boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi‎

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/*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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xiao_d: connector {
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compatible = "seeed,xiao-gpio";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <0 0 &gpio1 4 0>, /* D0 */
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<1 0 &gpio1 5 0>, /* D1 */
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<2 0 &gpio1 6 0>, /* D2 */
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<3 0 &gpio1 7 0>, /* D3 */
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<4 0 &gpio1 10 0>, /* D4 */
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<5 0 &gpio1 11 0>, /* D5 */
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<6 0 &gpio2 8 0>, /* D6 */
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<7 0 &gpio2 7 0>, /* D7 */
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<8 0 &gpio2 1 0>, /* D8 */
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<9 0 &gpio2 4 0>, /* D9 */
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<10 0 &gpio2 2 0>; /* D10 */
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};
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};
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xiao_i2c: &i2c22 {};
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xiao_serial: &uart21 {};
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xiao_adc: &adc {};
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xiao_spi: &spi00 {};

‎boards/seeed/xiao_nrf54l15/support/99-xiao-nrf54l15.rules‎

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# 2886:0066 Seeed SAMD Xiao-nRF54L15 CMSIS-DAP
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SUBSYSTEM=="usb", ATTR{idVendor}=="2886", ATTR{idProduct}=="0066", MODE:="666"
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# If you share your linux system with other users, or just don't like the
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# idea of write permission for everybody, you can replace MODE:="0666" with
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# OWNER:="yourusername" to create the device owned by you, or with
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# GROUP:="somegroupname" and mange access using standard unix groups.

‎boards/seeed/xiao_nrf54l15/support/openocd.cfg‎

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# SPDX-License-Identifier: Apache-2.0
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if {[info exists env(OPENOCD_INTERFACE)]} {
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set INTERFACE $env(OPENOCD_INTERFACE)
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} else {
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# By default connect over Debug USB port using the CMSIS-DAP interface
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set INTERFACE "cmsis-dap"
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}
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source [find interface/$INTERFACE.cfg]
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set _CHIPNAME nrf54l
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# Work-area is a space in RAM used for flash programming, by default use 16 KiB.
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x6ba02477
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}
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# Multidrop instance ID should be configurable by FW in TAD TINSTANCE register.
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# Writes to the register are ignored due to a silicon erratum.
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if { [info exists SWD_INSTANCE_ID] } {
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set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
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} else {
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set _SWD_INSTANCE_ID 0
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}
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transport select swd
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swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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if { [info exists SWD_MULTIDROP] } {
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x001c0289 -instance-id $_SWD_INSTANCE_ID
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} else {
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# Create target for the AUX access port (AUX-AP).
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target create $_CHIPNAME.aux mem_ap -dap $_CHIPNAME.dap -ap-num 1
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# AUX-AP is accessible only if CSW Prot[0] bit (Data Access) is set
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$_CHIPNAME.dap apsel 1
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$_CHIPNAME.dap apcsw 0x01000000 0x01000000
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adapter speed 1000
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# Use main processor as default target.
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targets $_TARGETNAME
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if {![using_hla]} {
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$_TARGETNAME cortex_m reset_config sysresetreq
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}
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proc nrf54l-load {file} {
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reset halt
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mww 0x5004b500 0x101
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load_image $file
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reset run
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}

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