merge master

Signed-off-by: LucasYuki <lucasyuki@yahoo.com.br>

Author: LucasYuki

.github/workflows/black.yaml

@@ -8,11 +8,5 @@ jobs:
     steps:
       - name: Checkout Code
         uses: actions/checkout@v3
-      - name: Run black (public repo)
-        if: "!github.event.repository.private"
+      - name: Run black
         uses: psf/black@stable
-      - name: Run black (private repo)
-        uses: psf/black@stable
-        if: github.event.repository.private
-        with:
-          version: "24.8.0"

src/cts/src/TritonCTS.cpp

@@ -1202,7 +1202,7 @@ bool TritonCTS::separateMacroRegSinks(
     if (iterm->isInputSignal() && inst->isPlaced()) {
       odb::dbMTerm* mterm = iterm->getMTerm();
       // Treat clock gaters like macro sink
-      if (hasInsertionDelay(inst, mterm) || !isSink(iterm)) {
+      if (hasInsertionDelay(inst, mterm) || !isSink(iterm) || inst->isBlock()) {
         macroSinks.emplace_back(inst, mterm);
       } else {
         registerSinks.emplace_back(inst, mterm);

src/cts/test/array.ok

@@ -8,76 +8,128 @@
                     BUF_X4
 [INFO CTS-0049] Characterization buffer is BUF_X4.
 [INFO CTS-0007] Net "clk" found for clock "clk".
-[INFO CTS-0010]  Clock net "clk" has 2475 sinks.
-[INFO CTS-0008] TritonCTS found 1 clock nets.
+[INFO CTS-0011]  Clock net "clk" for macros has 225 sinks.
+[INFO CTS-0011]  Clock net "clk_regs" for registers has 2250 sinks.
+[INFO CTS-0008] TritonCTS found 2 clock nets.
 [INFO CTS-0097] Characterization used 1 buffer(s) types.
 [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used.
 [INFO CTS-0027] Generating H-Tree topology for net clk.
-[INFO CTS-0028]  Total number of sinks: 2475.
+[INFO CTS-0028]  Total number of sinks: 225.
 [INFO CTS-0029]  Sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um.
 [INFO CTS-0030]  Number of static layers: 0.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
-[INFO CTS-0204] A clustering solution was found from clustering size of 30 and clustering diameter of 100.
+[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100.
 [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering.
-[INFO CTS-0019]  Total number of sinks after clustering: 279.
-[INFO CTS-0024]  Normalized sink region: [(1.43857, 3.42643), (661.439, 704.276)].
+[INFO CTS-0019]  Total number of sinks after clustering: 225.
+[INFO CTS-0024]  Normalized sink region: [(1.43857, 44.2757), (661.439, 704.276)].
 [INFO CTS-0025]     Width:  660.0000.
-[INFO CTS-0026]     Height: 700.8493.
+[INFO CTS-0026]     Height: 660.0000.
+ Level 1
+    Direction: Horizontal
+    Sinks per sub-region: 113
+    Sub-region size: 330.0000 X 660.0000
+[INFO CTS-0034]     Segment length (rounded): 166.
+ Level 2
+    Direction: Vertical
+    Sinks per sub-region: 57
+    Sub-region size: 330.0000 X 330.0000
+[INFO CTS-0034]     Segment length (rounded): 164.
+ Level 3
+    Direction: Horizontal
+    Sinks per sub-region: 29
+    Sub-region size: 165.0000 X 330.0000
+[INFO CTS-0034]     Segment length (rounded): 82.
+ Level 4
+    Direction: Vertical
+    Sinks per sub-region: 15
+    Sub-region size: 165.0000 X 165.0000
+[INFO CTS-0034]     Segment length (rounded): 82.
+ Level 5
+    Direction: Horizontal
+    Sinks per sub-region: 8
+    Sub-region size: 82.5000 X 165.0000
+[INFO CTS-0034]     Segment length (rounded): 42.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 225.
+[INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used.
+[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
+[INFO CTS-0028]  Total number of sinks: 2250.
+[INFO CTS-0029]  Sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um.
+[INFO CTS-0030]  Number of static layers: 0.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100.
+[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering.
+[INFO CTS-0019]  Total number of sinks after clustering: 227.
+[INFO CTS-0024]  Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)].
+[INFO CTS-0025]     Width:  471.4286.
+[INFO CTS-0026]     Height: 668.2000.
  Level 1
     Direction: Vertical
-    Sinks per sub-region: 140
-    Sub-region size: 660.0000 X 350.4246
-[INFO CTS-0034]     Segment length (rounded): 176.
+    Sinks per sub-region: 114
+    Sub-region size: 471.4286 X 334.1000
+[INFO CTS-0034]     Segment length (rounded): 168.
  Level 2
     Direction: Horizontal
-    Sinks per sub-region: 70
-    Sub-region size: 330.0000 X 350.4246
-[INFO CTS-0034]     Segment length (rounded): 166.
+    Sinks per sub-region: 57
+    Sub-region size: 235.7143 X 334.1000
+[INFO CTS-0034]     Segment length (rounded): 118.
  Level 3
     Direction: Vertical
-    Sinks per sub-region: 35
-    Sub-region size: 330.0000 X 175.2123
-[INFO CTS-0034]     Segment length (rounded): 88.
+    Sinks per sub-region: 29
+    Sub-region size: 235.7143 X 167.0500
+[INFO CTS-0034]     Segment length (rounded): 84.
  Level 4
     Direction: Horizontal
-    Sinks per sub-region: 18
-    Sub-region size: 165.0000 X 175.2123
-[INFO CTS-0034]     Segment length (rounded): 82.
+    Sinks per sub-region: 15
+    Sub-region size: 117.8572 X 167.0500
+[INFO CTS-0034]     Segment length (rounded): 58.
  Level 5
     Direction: Vertical
-    Sinks per sub-region: 9
-    Sub-region size: 165.0000 X 87.6062
-[INFO CTS-0034]     Segment length (rounded): 44.
+    Sinks per sub-region: 8
+    Sub-region size: 117.8572 X 83.5250
+[INFO CTS-0034]     Segment length (rounded): 42.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
-[INFO CTS-0035]  Number of sinks covered: 279.
-[INFO CTS-0018]     Created 231 clock buffers.
+[INFO CTS-0035]  Number of sinks covered: 227.
+[INFO CTS-0018]     Created 135 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 18.
-[INFO CTS-0013]     Maximum number of buffers in the clock path: 19.
-[INFO CTS-0015]     Created 231 clock nets.
-[INFO CTS-0016]     Fanout distribution for the current clock = 2:1, 5:1, 6:1, 7:6, 8:11, 9:7, 10:8, 11:3, 12:2, 14:2, 15:1, 19:1, 20:3, 21:36, 30:45..
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 18.
+[INFO CTS-0015]     Created 135 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 3:1, 5:3, 6:7, 7:3, 8:18..
+[INFO CTS-0017]     Max level of the clock tree: 5.
+[INFO CTS-0018]     Created 366 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 17.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 17.
+[INFO CTS-0015]     Created 366 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230..
 [INFO CTS-0017]     Max level of the clock tree: 5.
 [INFO CTS-0098] Clock net "clk"
-[INFO CTS-0099]  Sinks 2537
-[INFO CTS-0100]  Leaf buffers 96
-[INFO CTS-0101]  Average sink wire length 9258.86 um
-[INFO CTS-0102]  Path depth 18 - 19
-[INFO CTS-0207]  Leaf load cells 62
+[INFO CTS-0099]  Sinks 225
+[INFO CTS-0100]  Leaf buffers 0
+[INFO CTS-0101]  Average sink wire length 9172.05 um
+[INFO CTS-0102]  Path depth 18 - 18
+[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0098] Clock net "clk_regs"
+[INFO CTS-0099]  Sinks 2254
+[INFO CTS-0100]  Leaf buffers 227
+[INFO CTS-0101]  Average sink wire length 4115.91 um
+[INFO CTS-0102]  Path depth 17 - 17
+[INFO CTS-0207]  Leaf load cells 4
 [INFO RSZ-0058] Using max wire length 693um.
-[INFO RSZ-0047] Found 31 long wires.
-[INFO RSZ-0048] Inserted 90 buffers in 31 nets.
+[INFO RSZ-0047] Found 50 long wires.
+[INFO RSZ-0048] Inserted 110 buffers in 50 nets.
 Placement Analysis
 ---------------------------------
-total displacement       2522.4 u
-average displacement        0.9 u
-max displacement          117.9 u
-original HPWL          132665.1 u
-legalized HPWL         133067.8 u
+total displacement       4076.9 u
+average displacement        1.3 u
+max displacement          151.8 u
+original HPWL          182660.1 u
+legalized HPWL         183422.8 u
 delta HPWL                    0 %
 
 Clock clk
-   1.24 source latency inst_1_1/clk ^
-  -1.07 target latency inst_2_1/clk ^
+   1.25 source latency inst_1_0/clk ^
+  -1.15 target latency inst_2_0/clk ^
    0.00 CRPR
 --------------
-   0.18 setup skew
+   0.10 setup skew
 

src/cts/test/array_no_blockages.ok

@@ -168,6 +168,24 @@ class FlexPA
   template <typename T>
   int genPinAccess(T* pin, frInstTerm* inst_term = nullptr);
 
+  /**
+   * @brief determines if the current access points are enough to say PA is done
+   * with this pin.
+   *
+   * for the access points to be considered enough there must exist a minimum of
+   * aps:
+   * 1. far enough from each other greater than the minimum specified in
+   * router_cfg.
+   * 2. far enough from the cell edge.
+   *
+   * @param aps the list of candidate access points
+   * @param inst_term terminal related to the pin
+   *
+   * @returns True if the current aps are enough for the pin
+   */
+  bool EnoughAccessPoints(std::vector<std::unique_ptr<frAccessPoint>>& aps,
+                          frInstTerm* inst_term);
+
   /**
    * @brief initializes the pin accesses of a given pin only considering a given
    * cost for both the lower and upper layer.
@@ -180,7 +198,7 @@ class FlexPA
    * @param lower_type lower layer access type
    * @param upper_type upper layer access type
    *
-   * @return if the initialization was sucessful
+   * @return if enough access points were found for the pin.
    */
   template <typename T>
   bool genPinAccessCostBounded(