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[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (llvm#164349)
XSfvfbfexp16e, XSfvfexp16e, and XSfvfexp32e are SiFive's vector exponential instruction extensions of BFloat16, F16, and F32, respectively. Spec: https://www.sifive.com/document-file/exponential-function-instruction-xsfvfexp32e-xsfvf XSfvfexpa and XSfvfexpa64e are SiFive's vector exponential approximation instruction extensions where the former supports F16 and F32 and the latter covers F64. These instructions approximate 2 raised to a fractional power. Spec: https://www.sifive.com/document-file/exponential-approximation-instruction-xsfvfexpa-ex This patch adds their corresponding features and MC supports. --------- Co-authored-by: Jesse Huang <[email protected]> Co-authored-by: Craig Topper <[email protected]>
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -190,6 +190,11 @@
190190
// CHECK-NEXT: xsfmm64t 0.6 'XSfmm64t' (TE=64 configuration)
191191
// CHECK-NEXT: xsfmmbase 0.6 'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)
192192
// CHECK-NEXT: xsfvcp 1.0 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)
193+
// CHECK-NEXT: xsfvfbfexp16e 0.5 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16)
194+
// CHECK-NEXT: xsfvfexp16e 0.5 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision)
195+
// CHECK-NEXT: xsfvfexp32e 0.5 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision)
196+
// CHECK-NEXT: xsfvfexpa 0.2 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)
197+
// CHECK-NEXT: xsfvfexpa64e 0.2 'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision)
193198
// CHECK-NEXT: xsfvfnrclipxfqf 1.0 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)
194199
// CHECK-NEXT: xsfvfwmaccqqq 1.0 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))
195200
// CHECK-NEXT: xsfvqmaccdod 1.0 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))

‎clang/test/Preprocessor/riscv-target-features-sifive.c‎

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@@ -5,6 +5,11 @@
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// CHECK-NOT: __riscv_xsfcease {{.*$}}
77
// CHECK-NOT: __riscv_xsfvcp {{.*$}}
8+
// CHECK-NOT: __riscv_xsfvfbfexp16e {{.*$}}
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// CHECK-NOT: __riscv_xsfvfexp16e {{.*$}}
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// CHECK-NOT: __riscv_xsfvfexp32e {{.*$}}
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// CHECK-NOT: __riscv_xsfvfexpa {{.*$}}
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// CHECK-NOT: __riscv_xsfvfexpa64e {{.*$}}
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// CHECK-NOT: __riscv_xsfvfnrclipxfqf {{.*$}}
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// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
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// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
@@ -38,6 +43,46 @@
3843
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s
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// CHECK-XSFVCP-EXT: __riscv_xsfvcp 1000000{{$}}
4045

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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfvfbfexp16e_zvfbfmin -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFBFEXP16E-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsfvfbfexp16e_zvfbfmin -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFBFEXP16E-EXT %s
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// CHECK-XSFVFBFEXP16E-EXT: __riscv_xsfvfbfexp16e 5000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfvfexp16e -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXP16E-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsfvfexp16e -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXP16E-EXT %s
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// CHECK-XSFVFEXP16E-EXT: __riscv_xsfvfexp16e 5000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfvfexp32e -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXP32E-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsfvfexp32e -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXP32E-EXT %s
68+
// CHECK-XSFVFEXP32E-EXT: __riscv_xsfvfexp32e 5000{{$}}
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70+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfvfexpa -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXPA-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsfvfexpa -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXPA-EXT %s
76+
// CHECK-XSFVFEXPA-EXT: __riscv_xsfvfexpa 2000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfvfexpa64e -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXPA64E-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
82+
// RUN: -march=rv64ixsfvfexpa64e -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFEXPA64E-EXT %s
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// CHECK-XSFVFEXPA64E-EXT: __riscv_xsfvfexpa64e 2000{{$}}
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4186
// RUN: %clang --target=riscv32-unknown-linux-gnu \
4287
// RUN: -march=rv32ixsfvfnrclipxfqf -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVFNRCLIPXFQF-EXT %s

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2406,7 +2406,8 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
24062406
}
24072407

24082408
bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
2409-
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa))
2409+
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa) ||
2410+
STI->hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))
24102411
return Error(
24112412
ErrorLoc,
24122413
"operand must be "

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -654,7 +654,10 @@ static constexpr FeatureBitset XqciFeatureGroup = {
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static constexpr FeatureBitset XSfVectorGroup = {
655655
RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
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RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
657-
RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
657+
RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase,
658+
RISCV::FeatureVendorXSfvfexpa, RISCV::FeatureVendorXSfvfexpa64e,
659+
RISCV::FeatureVendorXSfvfbfexp16e, RISCV::FeatureVendorXSfvfexp16e,
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RISCV::FeatureVendorXSfvfexp32e};
658661
static constexpr FeatureBitset XSfSystemGroup = {
659662
RISCV::FeatureVendorXSiFivecdiscarddlone,
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RISCV::FeatureVendorXSiFivecflushdlone,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp‎

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@@ -220,7 +220,8 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
220220
if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
221221
RISCVVType::getSEW(Imm) > 64 ||
222222
(RISCVVType::isAltFmt(Imm) &&
223-
!STI.hasFeature(RISCV::FeatureStdExtZvfbfa)) ||
223+
!(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
224+
STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) ||
224225
(Imm >> 9) != 0) {
225226
O << formatImm(Imm);
226227
return;

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1335,6 +1335,44 @@ def HasVendorXSfvfnrclipxfqf
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AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
13361336
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
13371337

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// Note: XSfvfbfexp16e depends on either Zvfbfmin _or_ Zvfbfa, which cannot be expressed here in
1339+
// TableGen. Instead, we check that in RISCVISAInfo.
1340+
def FeatureVendorXSfvfbfexp16e
1341+
: RISCVExtension<0, 5,
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"SiFive Vector Floating-Point Exponential Function Instruction, BFloat16">;
1343+
def HasVendorXSfvfbfexp16e : Predicate<"Subtarget->hasVendorXSfvfbfexp16e()">;
1344+
1345+
def FeatureVendorXSfvfexp16e
1346+
: RISCVExtension<0, 5,
1347+
"SiFive Vector Floating-Point Exponential Function Instruction, Half Precision",
1348+
[FeatureStdExtZvfh]>;
1349+
def HasVendorXSfvfexp16e : Predicate<"Subtarget->hasVendorXSfvfexp16e()">;
1350+
1351+
def FeatureVendorXSfvfexp32e
1352+
: RISCVExtension<0, 5,
1353+
"SiFive Vector Floating-Point Exponential Function Instruction, Single Precision",
1354+
[FeatureStdExtZve32f]>;
1355+
def HasVendorXSfvfexp32e : Predicate<"Subtarget->hasVendorXSfvfexp32e()">;
1356+
1357+
def HasVendorXSfvfexpAnyFloat : Predicate<"Subtarget->hasVendorXSfvfexp16e() || Subtarget->hasVendorXSfvfexp32e()">;
1358+
def HasVendorXSfvfexpAny : Predicate<"Subtarget->hasVendorXSfvfbfexp16e() || Subtarget->hasVendorXSfvfexp16e() || Subtarget->hasVendorXSfvfexp32e()">,
1359+
AssemblerPredicate<(any_of FeatureVendorXSfvfbfexp16e, FeatureVendorXSfvfexp16e, FeatureVendorXSfvfexp32e),
1360+
"'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)">;
1361+
1362+
def FeatureVendorXSfvfexpa
1363+
: RISCVExtension<0, 2,
1364+
"SiFive Vector Floating-Point Exponential Approximation Instruction",
1365+
[FeatureStdExtZve32f]>;
1366+
def HasVendorXSfvfexpa : Predicate<"Subtarget->hasVendorXSfvfexpa()">,
1367+
AssemblerPredicate<(all_of FeatureVendorXSfvfexpa),
1368+
"'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)">;
1369+
1370+
def FeatureVendorXSfvfexpa64e
1371+
: RISCVExtension<0, 2,
1372+
"SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision",
1373+
[FeatureVendorXSfvfexpa, FeatureStdExtZve64d]>;
1374+
def HasVendorXSfvfexpa64e : Predicate<"Subtarget->hasVendorXSfvfexpa64e()">;
1375+
13381376
def FeatureVendorXSiFivecdiscarddlone
13391377
: RISCVExtension<1, 0,
13401378
"SiFive sf.cdiscard.d.l1 Instruction", []>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td‎

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Original file line numberDiff line numberDiff line change
@@ -217,6 +217,14 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
217217
defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>;
218218
}
219219

220+
let Predicates = [HasVendorXSfvfexpAny], DecoderNamespace = "XSfvector" in {
221+
def SF_VFEXP_V : VALUVs2<0b010011, 0b00111, OPFVV, "sf.vfexp.v">;
222+
}
223+
224+
let Predicates = [HasVendorXSfvfexpa], DecoderNamespace = "XSfvector" in {
225+
def SF_VFEXPA_V : VALUVs2<0b010011, 0b00110, OPFVV, "sf.vfexpa.v">;
226+
}
227+
220228
let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvector",
221229
DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {
222230
def SF_VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -765,6 +765,12 @@ Error RISCVISAInfo::checkDependency() {
765765
if (HasZvl && !HasVector)
766766
return getExtensionRequiresError("zvl*b", "v' or 'zve*");
767767

768+
if (Exts.count("xsfvfbfexp16e") &&
769+
!(Exts.count("zvfbfmin") || Exts.count("zvfbfa")))
770+
return createStringError(errc::invalid_argument,
771+
"'xsfvfbfexp16e' requires 'zvfbfmin' or "
772+
"'zvfbfa' extension to also be specified");
773+
768774
if (HasD && (HasC || Exts.count("zcd")))
769775
for (auto Ext : ZcdOverlaps)
770776
if (Exts.count(Ext.str()))

‎llvm/test/CodeGen/RISCV/features-info.ll‎

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@@ -217,6 +217,11 @@
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; CHECK-NEXT: xsfmm64t - 'XSfmm64t' (TE=64 configuration).
218218
; CHECK-NEXT: xsfmmbase - 'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero).
219219
; CHECK-NEXT: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions).
220+
; CHECK-NEXT: xsfvfbfexp16e - 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16).
221+
; CHECK-NEXT: xsfvfexp16e - 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision).
222+
; CHECK-NEXT: xsfvfexp32e - 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision).
223+
; CHECK-NEXT: xsfvfexpa - 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction).
224+
; CHECK-NEXT: xsfvfexpa64e - 'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision).
220225
; CHECK-NEXT: xsfvfnrclipxfqf - 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions).
221226
; CHECK-NEXT: xsfvfwmaccqqq - 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4)).
222227
; CHECK-NEXT: xsfvqmaccdod - 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)).

‎llvm/test/MC/RISCV/xsfvfexp.s‎

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@@ -0,0 +1,29 @@
1+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexp32e %s \
2+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
4+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp32e %s \
6+
# RUN: | llvm-objdump -d --mattr=+xsfvfexp32e - \
7+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
8+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp32e %s \
9+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
10+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexp16e %s \
11+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
12+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp16e %s \
13+
# RUN: | llvm-objdump -d --mattr=+xsfvfexp16e - \
14+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
15+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp16e %s \
16+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
17+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvfbfmin,+xsfvfbfexp16e %s \
18+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
19+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvfbfmin,+xsfvfbfexp16e %s \
20+
# RUN: | llvm-objdump -d --mattr=+xsfvfbfexp16e - \
21+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
22+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvfbfmin,+xsfvfbfexp16e %s \
23+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
24+
25+
sf.vfexp.v v2, v5, v0.t
26+
# CHECK-INST: sf.vfexp.v v2, v5, v0.t
27+
# CHECK-ENCODING: [0x57,0x91,0x53,0x4c]
28+
# CHECK-ERROR: instruction requires the following: 'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction){{$}}
29+
# CHECK-UNKNOWN: 4c539157 <unknown>

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