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Removed a bunch of commented-out code, and cleaned up formatting for divider32, multiply32, and shifter32.
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3 files changed

+47
-77
lines changed

3 files changed

+47
-77
lines changed

src/vhdl/divider32.vhdl

Lines changed: 20 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -80,16 +80,6 @@ architecture neo_gregorian of divider32 is
8080
end function count_leading_zeros;
8181
begin
8282

83-
-- instance "fast_divide_1"
84-
-- fast_divide_1: entity work.fast_divide
85-
-- port map (
86-
-- clock => clock,
87-
-- n => a,
88-
-- d => b,
89-
-- q => q,
90-
-- start_over => start_over,
91-
-- busy => busy);
92-
9383
process (clock) is
9484
variable temp64 : unsigned(73 downto 0) := to_unsigned(0,74);
9585
variable temp96 : unsigned(105 downto 0) := to_unsigned(0,106);
@@ -279,33 +269,27 @@ begin
279269
start_over <= '0';
280270
end if;
281271

282-
-- Even units do addition, odd ones do subtraction
283-
-- if (unit mod 2) = 0 then
284-
s <= unsigned((a(31) & a) + (b(31) & b));
285-
-- else
286-
-- s <= unsigned((a(31) & a)-(b(31) & b));
287-
-- end if;
272+
-- Compute sum of inputs
273+
s <= unsigned((a(31) & a) + (b(31) & b));
288274

289-
-- Display output value when requested, and tri-state outputs otherwise
290-
-- if output_select = unit then
291-
if do_add='1' then
292-
-- Output sign-extended 33 bit addition result
293-
output_value(63 downto 33) <= (others => s(32));
294-
output_value(32 downto 0) <= s;
295-
report "MATH: Unit #" & integer'image(unit)
296-
& " outputting addition sum $" & to_hstring(s);
297-
elsif do_mult = '1' then
298-
output_value <= shift_right(p, to_integer(mult_shift & "000"));
299-
report "MATH: Unit #" & integer'image(unit)
300-
& " outputting multiplication product $" & to_hstring(p);
301-
else
302-
output_value <= q;
303-
report "MATH: Unit #" & integer'image(unit)
304-
& " outputting division quotient $" & to_hstring(q);
305-
end if;
306-
-- else
307-
-- output_value <= (others => 'Z');
308-
-- end if;
275+
-- Output result, stored in output register on the CPU side
276+
if do_add='1' then
277+
-- Output sign-extended 33 bit addition result
278+
output_value(63 downto 33) <= (others => s(32));
279+
output_value(32 downto 0) <= s;
280+
report "MATH: Unit #" & integer'image(unit)
281+
& " outputting addition sum $" & to_hstring(s);
282+
elsif do_mult = '1' then
283+
-- Output product shifted by multiplication shift
284+
output_value <= shift_right(p, to_integer(mult_shift & "000"));
285+
report "MATH: Unit #" & integer'image(unit)
286+
& " outputting multiplication product $" & to_hstring(p);
287+
else
288+
-- Output quotient and fractional part
289+
output_value <= q;
290+
report "MATH: Unit #" & integer'image(unit)
291+
& " outputting division quotient $" & to_hstring(q);
292+
end if;
309293
end if;
310294
end process;
311295
end neo_gregorian;

src/vhdl/multiply32.vhdl

Lines changed: 16 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -90,29 +90,23 @@ begin
9090
p3 <= p2;
9191
p4 <= p3;
9292
p <= p4;
93-
-- Even units do addition, odd ones do subtraction
94-
-- if (unit mod 2) = 0 then
95-
s <= unsigned((a(31) & a)+(b(31) & b));
96-
-- else
97-
-- s <= unsigned((a(31) & a)-(b(31) & b));
98-
-- end if;
9993

100-
-- Display output value when requested, and tri-state outputs otherwise
101-
-- if output_select = unit then
102-
if do_add='1' then
103-
-- Output sign-extended 33 bit addition result
104-
output_value(63 downto 33) <= (others => s(32));
105-
output_value(32 downto 0) <= s;
106-
report "MATH: Unit #" & integer'image(unit)
107-
& " outputting addition sum $" & to_hstring(s);
108-
else
109-
output_value <= shift_right(unsigned(p), to_integer(output_shift & "000"));
110-
-- report "MATH: Unit #" & integer'image(unit)
111-
-- & " outputting multiplication product $" & to_hstring(unsigned(p));
112-
end if;
113-
-- else
114-
-- output_value <= (others => 'Z');
115-
-- end if;
94+
-- Calculate sum of inputs
95+
s <= unsigned((a(31) & a)+(b(31) & b));
96+
97+
-- Output result, stored in output register on the CPU side
98+
if do_add='1' then
99+
-- Output sign-extended 33 bit addition result
100+
output_value(63 downto 33) <= (others => s(32));
101+
output_value(32 downto 0) <= s;
102+
-- report "MATH: Unit #" & integer'image(unit)
103+
-- & " outputting addition sum $" & to_hstring(s);
104+
else
105+
-- Output product shifted by the output shift
106+
output_value <= shift_right(unsigned(p), to_integer(output_shift & "000"));
107+
-- report "MATH: Unit #" & integer'image(unit)
108+
-- & " outputting multiplication product $" & to_hstring(unsigned(p));
109+
end if;
116110
end if;
117111
end process;
118112
end neo_gregorian;

src/vhdl/shifter32.vhdl

Lines changed: 11 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -69,13 +69,8 @@ begin
6969
end if;
7070
end if;
7171

72-
-- Calculate the result
73-
-- Even units do addition, odd ones do subtraction
74-
-- if (unit mod 2) = 0 then
75-
s <= unsigned((a(31) & a)+(b(31) & b));
76-
-- else
77-
-- s <= unsigned((a(31) & a)-(b(31) & b));
78-
-- end if;
72+
-- Calculate sum of inputs
73+
s <= unsigned((a(31) & a)+(b(31) & b));
7974

8075
if b(7 downto 0) = x"00" then
8176
p(63 downto 32) <= (others => '0');
@@ -93,18 +88,15 @@ begin
9388
end if;
9489
end if;
9590

96-
-- Display output value when requested, and tri-state outputs otherwise
97-
-- if output_select = unit then
98-
if do_add='1' then
99-
-- Output sign-extended 33 bit addition result
100-
output_value(63 downto 33) <= (others => s(32));
101-
output_value(32 downto 0) <= s;
102-
else
103-
output_value <= p;
104-
end if;
105-
-- else
106-
-- output_value <= (others => 'Z');
107-
-- end if;
91+
-- Output result, stored in output register on the CPU side
92+
if do_add='1' then
93+
-- Output sign-extended 33 bit addition result
94+
output_value(63 downto 33) <= (others => s(32));
95+
output_value(32 downto 0) <= s;
96+
else
97+
-- Output shifted result
98+
output_value <= p;
99+
end if;
108100
end if;
109101
end process;
110102
end neo_gregorian;

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