Skip to content

Commit 9a2b3dd

Browse files
AnandAnand
authored andcommitted
Removing whitespace + regression test bug caught in toolchain (lint)
1 parent c032ee9 commit 9a2b3dd

File tree

6 files changed

+105
-49
lines changed

6 files changed

+105
-49
lines changed

src/simulation/m_cbc.fpp

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -135,14 +135,11 @@ module m_cbc
135135
!$acc declare create(dj, bcxb, bcxe, bcyb, bcye, bczb, bcze, cbc_dir, cbc_loc)
136136

137137
real(kind(0d0)) :: ux_in, ux_out, vx_in, vx_out, wx_in, wx_out, presx_in, presx_out, Delx_in, Delx_out
138-
139138
real(kind(0d0)) :: uy_in, uy_out, vy_in, vy_out, wy_in, wy_out, presy_in, presy_out, Dely_in, Dely_out
140-
141139
real(kind(0d0)) :: uz_in, uz_out, vz_in, vz_out, wz_in, wz_out, presz_in, presz_out, Delz_in, Delz_out
142-
143-
!$acc declare create(ux_in, ux_out, vx_in, vx_out, wx_in, wx_out, presx_in, presx_out, Delx_in, Delx_out)
144-
!$acc declare create(uy_in, uy_out, vy_in, vy_out, wy_in, wy_out, presy_in, presy_out, Dely_in, Dely_out)
145-
!$acc declare create(uz_in, uz_out, vz_in, vz_out, wz_in, wz_out, presz_in, presz_out, Delz_in, Delz_out)
140+
!$acc declare create(ux_in, ux_out, vx_in, vx_out, wx_in, wx_out, presx_in, presx_out, Delx_in, Delx_out)
141+
!$acc declare create(uy_in, uy_out, vy_in, vy_out, wy_in, wy_out, presy_in, presy_out, Dely_in, Dely_out)
142+
!$acc declare create(uz_in, uz_out, vz_in, vz_out, wz_in, wz_out, presz_in, presz_out, Delz_in, Delz_out)
146143

147144
#ifdef CRAY_ACC_WAR
148145
@:CRAY_DECLARE_GLOBAL(real(kind(0d0)), dimension(:), alpha_rhox_in, alphax_in)
@@ -452,7 +449,6 @@ contains
452449
@:ALLOCATE_GLOBAL(alphax_in(1:num_fluids), alphay_in(1:num_fluids), alphaz_in(1:num_fluids))
453450

454451
#:for CBC_DIR, XYZ in [(1, 'x'), (2, 'y'), (3, 'z')]
455-
456452
if (${CBC_DIR}$ == 1) then
457453
u${XYZ}$_in = bc_${XYZ}$%u_in
458454
v${XYZ}$_in = bc_${XYZ}$%v_in
@@ -463,7 +459,6 @@ contains
463459
Del${XYZ}$_in = maxval(dx)
464460
Del${XYZ}$_out = maxval(dx)
465461
else if (${CBC_DIR}$ == 2) then
466-
467462
u${XYZ}$_in = bc_${XYZ}$%v_in
468463
v${XYZ}$_in = bc_${XYZ}$%u_in
469464
w${XYZ}$_in = bc_${XYZ}$%w_in
@@ -486,7 +481,6 @@ contains
486481
Del${XYZ}$_out = maxval(dz)
487482
end if
488483
end if
489-
490484
pres${XYZ}$_in = bc_${XYZ}$%pres_in
491485
pres${XYZ}$_out = bc_${XYZ}$%pres_out
492486
do i = 1, num_fluids
@@ -496,7 +490,6 @@ contains
496490
!$acc update device(u${XYZ}$_in, v${XYZ}$_in, w${XYZ}$_in, u${XYZ}$_out, v${XYZ}$_out, w${XYZ}$_out)
497491
!$acc update device(pres${XYZ}$_in, pres${XYZ}$_out, alpha_rho${XYZ}$_in, alpha${XYZ}$_in)
498492
!$acc update device(Del${XYZ}$_in, Del${XYZ}$_out)
499-
500493
#:endfor
501494

502495
end subroutine s_initialize_cbc_module
@@ -943,7 +936,6 @@ contains
943936
call s_compute_nonreflecting_subsonic_buffer_L(lambda, L, rho, c, mf, dalpha_rho_ds, dpres_ds, dvel_ds, dadv_ds)
944937
else if ((cbc_loc == -1 .and. bc${XYZ}$b == -7) .or. (cbc_loc == 1 .and. bc${XYZ}$e == -7)) then
945938
call s_compute_nonreflecting_subsonic_inflow_L(lambda, L, rho, c, mf, dalpha_rho_ds, dpres_ds, dvel_ds, dadv_ds)
946-
947939
!Add GRCBC for Subsonic Inflow
948940
if (bc_${XYZ}$%grcbc_in) then
949941
!$acc loop seq
@@ -964,7 +956,6 @@ contains
964956
end if
965957
else if ((cbc_loc == -1 .and. bc${XYZ}$b == -8) .or. (cbc_loc == 1 .and. bc${XYZ}$e == -8)) then
966958
call s_compute_nonreflecting_subsonic_outflow_L(lambda, L, rho, c, mf, dalpha_rho_ds, dpres_ds, dvel_ds, dadv_ds)
967-
968959
!Add GRCBC for Subsonic Outflow (Pressure)
969960
if (bc_${XYZ}$%grcbc_out) then
970961
L(advxe) = c*(1d0 - Ma)*(pres - pres${XYZ}$_out)/Del${XYZ}$_out
@@ -974,7 +965,6 @@ contains
974965
L(advxe) = L(advxe) + rho*c**2d0*(1d0 - Ma)*(vel(dir_idx(1)) + u${XYZ}$_out*sign(1, cbc_loc))/Del${XYZ}$_out
975966
end if
976967
end if
977-
978968
else if ((cbc_loc == -1 .and. bc${XYZ}$b == -9) .or. (cbc_loc == 1 .and. bc${XYZ}$e == -9)) then
979969
call s_compute_force_free_subsonic_outflow_L(lambda, L, rho, c, mf, dalpha_rho_ds, dpres_ds, dvel_ds, dadv_ds)
980970
else if ((cbc_loc == -1 .and. bc${XYZ}$b == -10) .or. (cbc_loc == 1 .and. bc${XYZ}$e == -10)) then

tests/872E17A1/golden-metadata.txt

Lines changed: 38 additions & 5 deletions
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

tests/872E17A1/golden.txt

Lines changed: 5 additions & 5 deletions
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

tests/EBBA071B/golden-metadata.txt

Lines changed: 41 additions & 8 deletions
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

tests/EBBA071B/golden.txt

Lines changed: 4 additions & 4 deletions
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

toolchain/mfc/test/cases.py

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -75,27 +75,27 @@ def alter_bcs(dimInfo):
7575
cases.append(define_case_d(stack, f"bc={bc}", get_bc_mods(bc, dimInfo)))
7676

7777
def alter_grcbc(dimInfo):
78-
if(len(dimInfo[0]) == 1):
79-
stack.push('', {'patch_icpp(1)%vel(1)' : 1.0, 'patch_icpp(2)%vel(1)' : 1.0, 'patch_icpp(3)%vel(1)' : 1.0,
78+
if len(dimInfo[0]) == 1:
79+
stack.push('', {'patch_icpp(1)%vel(1)':1.0, 'patch_icpp(2)%vel(1)':1.0, 'patch_icpp(3)%vel(1)':1.0,
8080
'bc_x%beg':-7, 'bc_x%end':-8, 'bc_x%grcbc_in':'T', 'bc_x%grcbc_out':'T', 'bc_x%grcbc_vel_out':'T',
81-
'bc_x%u_in':1.0, 'bc_x%v_in':0.0, 'bc_x%w_in':0.0, 'bc_x%u_out':1.0, 'bc_x%v_in':0.0, 'bc_x%w_in':0.0,
82-
'bc_x%pres_in':1.0, 'bc_x%pres_out':1.0, 'bc_x%alpha_in(1)':1.0, 'bc_x%alpha_rho_in(1)':1.0 })
81+
'bc_x%u_in':1.0, 'bc_x%v_in':0.0, 'bc_x%w_in':0.0, 'bc_x%u_out':1.0, 'bc_x%v_out':0.0, 'bc_x%w_out':0.0,
82+
'bc_x%pres_in':1.0, 'bc_x%pres_out':1.0, 'bc_x%alpha_in(1)':1.0, 'bc_x%alpha_rho_in(1)':1.0})
8383
cases.append(define_case_d(stack, [f"grcbc"],{}))
8484
stack.pop()
85-
elif(len(dimInfo[0]) == 2):
86-
stack.push('', {'patch_icpp(1)%vel(2)' : 1.0, 'patch_icpp(2)%vel(2)' : 1.0, 'patch_icpp(3)%vel(2)' : 1.0,
85+
elif len(dimInfo[0]) == 2:
86+
stack.push('', {'patch_icpp(1)%vel(2)':1.0, 'patch_icpp(2)%vel(2)':1.0, 'patch_icpp(3)%vel(2)':1.0,
8787
'bc_y%beg':-7, 'bc_y%end':-8, 'bc_y%grcbc_in':'T', 'bc_y%grcbc_out':'T', 'bc_y%grcbc_vel_out':'T',
88-
'bc_y%u_in':0.0, 'bc_y%v_in':1.0, 'bc_y%w_in':0.0, 'bc_y%u_out':0.0, 'bc_y%v_in':1.0, 'bc_y%w_in':0.0,
89-
'bc_y%pres_in':1.0, 'bc_y%pres_out':1.0, 'bc_y%alpha_in(1)':1.0, 'bc_y%alpha_rho_in(1)':1.0 })
88+
'bc_y%u_in':0.0, 'bc_y%v_in':1.0, 'bc_y%w_in':0.0, 'bc_y%u_out':0.0, 'bc_y%v_out':1.0, 'bc_y%w_out':0.0,
89+
'bc_y%pres_in':1.0, 'bc_y%pres_out':1.0, 'bc_y%alpha_in(1)':1.0, 'bc_y%alpha_rho_in(1)':1.0})
9090
cases.append(define_case_d(stack, [f"grcbc"],{}))
91-
stack.pop()
92-
elif(len(dimInfo[0]) == 3):
93-
stack.push('', {'patch_icpp(1)%vel(3)' : 1.0, 'patch_icpp(2)%vel(3)' : 1.0, 'patch_icpp(3)%vel(3)' : 1.0,
91+
stack.pop()
92+
elif len(dimInfo[0]) == 3:
93+
stack.push('', {'patch_icpp(1)%vel(3)':1.0, 'patch_icpp(2)%vel(3)':1.0, 'patch_icpp(3)%vel(3)':1.0,
9494
'bc_z%beg':-7, 'bc_z%end':-8, 'bc_z%grcbc_in':'T', 'bc_z%grcbc_out':'T', 'bc_z%grcbc_vel_out':'T',
95-
'bc_z%u_in':0.0, 'bc_z%v_in':0.0, 'bc_z%w_in':1.0, 'bc_z%u_out':0.0, 'bc_z%v_in':0.0, 'bc_z%w_in':1.0,
96-
'bc_z%pres_in':1.0, 'bc_z%pres_out':1.0, 'bc_z%alpha_in(1)':1.0, 'bc_z%alpha_rho_in(1)':1.0 })
95+
'bc_z%u_in':0.0, 'bc_z%v_in':0.0, 'bc_z%w_in':1.0, 'bc_z%u_out':0.0, 'bc_z%v_out':0.0, 'bc_z%w_out':1.0,
96+
'bc_z%pres_in':1.0, 'bc_z%pres_out':1.0, 'bc_z%alpha_in(1)':1.0, 'bc_z%alpha_rho_in(1)':1.0})
9797
cases.append(define_case_d(stack, [f"grcbc"],{}))
98-
stack.pop()
98+
stack.pop()
9999

100100
def alter_capillary():
101101
stack.push('', {'patch_icpp(1)%cf_val':1, 'patch_icpp(2)%cf_val':0, 'patch_icpp(3)%cf_val':1,

0 commit comments

Comments
 (0)