Implement ADD and SUB instructions

Author: outercloudstudio

documentation/Modules/Hart.md

@@ -7,4 +7,58 @@ The instruction at the program pointer is requested from memory.
 ### Stage 1
 The instruction is available from memory and the decoder is now emitting the decoded instruction. We store the decoded instructions in buffers for access in later stages. Most instructions can simply execute in this stage and then set the stage counter back to 0 and increase the program pointer.
 ## Stage 2
-Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests the info from memory and then in stage 2 it takes the value from memory and writes it to the register.
+Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests the info from memory and then in stage 2 it takes the value from memory and writes it to the register.
+## Implemented Instructions
+### Main Integer Instructions
+- [x] LUI
+- [x] AUIPC
+- [x] ADDI
+- [x] SLTI
+- [x] SLTIU
+- [x] XORI
+- [x] ORI
+- [x] ANDI
+- [ ] SLLI
+- [ ] SRLI
+- [ ] SRAI
+- [ ] ADD
+- [ ] SUB
+- [ ] SLL
+- [ ] SLT
+- [ ] SLTU
+- [ ] XOR
+- [ ] SRL
+- [ ] SRA
+- [ ] OR
+- [ ] AND
+- [ ] LB
+- [ ] LH
+- [x] LW
+- [ ] LBU
+- [ ] LHU
+- [ ] SB
+- [ ] SH
+- [x] SW
+- [ ] JAL
+- [ ] JALR
+- [ ] BEQ
+- [ ] BNE
+- [ ] BLT
+- [ ] BGE
+- [ ] BLTU
+- [ ] BGEU
+### Other Integer Instructions
+- [ ] FENCE
+- [ ] FENCEI
+- [ ] ECALL
+- [ ] EBREAK
+- [ ] SRET
+- [ ] MRET
+- [ ] WFI
+- [ ] SFENCEVMA
+- [ ] CSRRW
+- [ ] CSRRS
+- [ ] CSRRC
+- [ ] CSRRWI
+- [ ] CSRRSI
+- [ ] CSRRCI

src/main/scala/RISCV/Main.scala

@@ -224,7 +224,7 @@ class Main() extends Module {
                     program_pointer := program_pointer + 1.U;
                     stage := 0.U;
 
-                    printf("[XORI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
+                    printf("[ORI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
                 }
 
                 // ANDI
@@ -238,7 +238,37 @@ class Main() extends Module {
                     program_pointer := program_pointer + 1.U;
                     stage := 0.U;
 
-                    printf("[XORI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
+                    printf("[ANDI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
+                }
+
+                // ADD
+                is("b0000000_000_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := registers.io.out_a + registers.io.out_b;
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[ADD] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
+                }
+
+                // SUB
+                is("b0110000_000_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := registers.io.out_a - registers.io.out_b;
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[SUB] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
                 }
             }
         }