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Add instruction formats to decoder
1 parent f52214a commit 169411e

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2 files changed

+54
-4
lines changed

2 files changed

+54
-4
lines changed

src/main/scala/RISCV/Decoder.scala

Lines changed: 50 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,21 @@ package RISCV
33
import chisel3._
44
import chisel3.util._
55
import _root_.circt.stage.ChiselStage
6+
import upickle.default
7+
8+
object InstructionFormat extends ChiselEnum {
9+
val R, I, S, B, U, J = Value
10+
}
11+
12+
object Opcode extends ChiselEnum {
13+
val ADDI = Value(0b0010011.U)
14+
val AUIPC = Value(0b0010111.U)
15+
val LUI = Value(0b0110111.U)
16+
}
617

718
/**
8-
* @param width Bit width (default: 32 bits)
9-
*/
19+
* @param width Bit width (default: 32 bits)
20+
*/
1021
class Decoder(val width: Int = 32) extends Module {
1122
val io = IO(new Bundle {
1223
val instruction = Input(UInt(32.W));
@@ -21,9 +32,45 @@ class Decoder(val width: Int = 32) extends Module {
2132
io.rs2 := io.instruction(24, 20);
2233
io.rd := io.instruction(11, 7);
2334

35+
val format = Wire(InstructionFormat());
36+
format := InstructionFormat.R;
37+
38+
val opcode = io.instruction(6,0);
39+
40+
switch(opcode) {
41+
is(Opcode.LUI.asUInt) { format := InstructionFormat.U; }
42+
is(Opcode.AUIPC.asUInt) { format := InstructionFormat.U; }
43+
is(Opcode.ADDI.asUInt) { format := InstructionFormat.I; }
44+
}
45+
2446
io.operation := 0.U;
25-
2647
io.immediate := 0.U;
48+
49+
switch(format){
50+
is(InstructionFormat.R) {
51+
io.operation := io.instruction(31,25) ## io.instruction(14,12) ## io.instruction(6,0);
52+
}
53+
is(InstructionFormat.I) {
54+
io.operation := io.instruction(14,12) ## io.instruction(6,0);
55+
io.immediate := io.instruction(31,31) ## 0.U(20.W) ## io.instruction(30,20);
56+
}
57+
is(InstructionFormat.S) {
58+
io.operation := io.instruction(14,12) ## io.instruction(6,0);
59+
io.immediate := io.instruction(31,31) ## 0.U(20.W) ## io.instruction(31,25) ## io.instruction(11,7);
60+
}
61+
is(InstructionFormat.B) {
62+
io.operation := io.instruction(14,12) ## io.instruction(6,0);
63+
io.immediate := io.instruction(31,31) ## 0.U(19.W) ## io.instruction(7,7) ## io.instruction(31,25) ## io.instruction(11,8) ## 0.U(1.W);
64+
}
65+
is(InstructionFormat.U) {
66+
io.operation := io.instruction(6,0);
67+
io.immediate := io.instruction(31,12) ## 0.U(12.W);
68+
}
69+
is(InstructionFormat.J) {
70+
io.operation := io.instruction(6,0);
71+
io.immediate := io.instruction(31,31) ## 0.U(11.W) ## io.instruction(19,12) ## io.instruction(20,20) ## io.instruction(30,21) ## 0.U(1.W);
72+
}
73+
}
2774
}
2875

2976
object Decoder extends App {

src/test/scala/RISCV/DecoderTest.scala

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,10 @@ import org.scalatest.matchers.must.Matchers
99
class DecoderTest extends AnyFreeSpec with Matchers with ChiselSim {
1010
"Decoder should pass tests" in {
1111
simulate(new Decoder()) { dut =>
12-
dut.io.instruction.poke(0.U);
12+
dut.io.instruction.poke(0b00000000000000000101_00001_0110111.U);
13+
dut.io.operation.expect(0b0000000_000_0110111.U);
14+
dut.io.rd.expect(0b00001.U);
15+
dut.io.immediate.expect(0b00000000000000000101_000000000000.U);
1316
}
1417
}
1518
}

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