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outercloudstudiooutercloudstudio
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fix memory reading
1 parent 8b0e176 commit 35e17ed

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2 files changed

+79
-43
lines changed

2 files changed

+79
-43
lines changed

‎src/main/scala/RISCV/Main.scala‎

Lines changed: 76 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ class Main() extends Module {
2828

2929
val program_pointer = RegInit(0.U(32.W));
3030

31-
val memory = SRAM(1024, UInt(32.W), 2, 1, 0);
31+
val memory = SRAM(1024, UInt(8.W), 8, 4, 0);
3232

3333
// Set up register file
3434
val registers = Module(new Registers())
@@ -61,19 +61,40 @@ class Main() extends Module {
6161
alu.io.b := 0.U(32.W)
6262

6363
val decoder = Module(new Decoder())
64-
decoder.io.instruction := memory.readPorts(0).data;
64+
decoder.io.instruction := memory.readPorts(3).data ## memory.readPorts(2).data ## memory.readPorts(1).data ## memory.readPorts(0).data;
6565

6666
val stage = RegInit(0.U(2.W)); // 0 - Load Instruction 1 - Execute Instruction A 2 - Execute Instruction B
6767

6868
memory.readPorts(0).enable := io.execute && stage === 0.U;
6969
memory.readPorts(0).address := program_pointer;
70-
71-
memory.readPorts(1).enable := false.B;
72-
memory.readPorts(1).address := 0.U;
70+
memory.readPorts(1).enable := io.execute && stage === 0.U;
71+
memory.readPorts(1).address := program_pointer + 1.U;
72+
memory.readPorts(2).enable := io.execute && stage === 0.U;
73+
memory.readPorts(2).address := program_pointer + 2.U;
74+
memory.readPorts(3).enable := io.execute && stage === 0.U;
75+
memory.readPorts(3).address := program_pointer + 3.U;
76+
77+
memory.readPorts(4).enable := false.B;
78+
memory.readPorts(4).address := 0.U;
79+
memory.readPorts(5).enable := false.B;
80+
memory.readPorts(5).address := 0.U;
81+
memory.readPorts(6).enable := false.B;
82+
memory.readPorts(6).address := 0.U;
83+
memory.readPorts(7).enable := false.B;
84+
memory.readPorts(7).address := 0.U;
7385

7486
memory.writePorts(0).enable := io.debug_write;
75-
memory.writePorts(0).address := io.debug_write_addressess;
87+
memory.writePorts(0).address := io.debug_write_addressess(7, 0);
7688
memory.writePorts(0).data := io.debug_write_data;
89+
memory.writePorts(1).enable := io.debug_write;
90+
memory.writePorts(1).address := io.debug_write_addressess + 1.U;
91+
memory.writePorts(1).data := io.debug_write_data(15,8);
92+
memory.writePorts(2).enable := io.debug_write;
93+
memory.writePorts(2).address := io.debug_write_addressess + 2.U;
94+
memory.writePorts(2).data := io.debug_write_data(23,16);
95+
memory.writePorts(3).enable := io.debug_write;
96+
memory.writePorts(3).address := io.debug_write_addressess + 3.U;
97+
memory.writePorts(3).data := io.debug_write_data(31,24);
7798

7899
val operation_buffer = RegInit(0.U(17.W));
79100
val rs1_buffer = RegInit(0.U(5.W));
@@ -85,7 +106,7 @@ class Main() extends Module {
85106
printf("Stage: %d\n", stage);
86107
printf("Operation: %b\n", decoder.io.operation);
87108
printf("Program Pointer: %d\n", program_pointer);
88-
printf("Data: %b\n", memory.readPorts(0).data);
109+
printf("Data: %b\n", memory.readPorts(3).data ## memory.readPorts(2).data ## memory.readPorts(1).data ## memory.readPorts(0).data);
89110
printf("Register 1: %b\n", registers.io.debug_1);
90111
printf("Register 2: %b\n", registers.io.debug_2);
91112

@@ -102,8 +123,14 @@ class Main() extends Module {
102123
is("b010_0000011".U) {
103124
registers.io.read_address_a := decoder.io.rs1;
104125

105-
memory.readPorts(1).enable := true.B;
106-
memory.readPorts(1).address := registers.io.out_a + decoder.io.immediate;
126+
memory.readPorts(4).enable := true.B;
127+
memory.readPorts(4).address := registers.io.out_a + decoder.io.immediate;
128+
memory.readPorts(5).enable := true.B;
129+
memory.readPorts(5).address := registers.io.out_a + decoder.io.immediate + 1.U;
130+
memory.readPorts(6).enable := true.B;
131+
memory.readPorts(6).address := registers.io.out_a + decoder.io.immediate + 2.U;
132+
memory.readPorts(7).enable := true.B;
133+
memory.readPorts(7).address := registers.io.out_a + decoder.io.immediate + 3.U;
107134

108135
printf("[LW] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
109136
}
@@ -115,9 +142,18 @@ class Main() extends Module {
115142

116143
memory.writePorts(0).enable := true.B;
117144
memory.writePorts(0).address := registers.io.out_a + decoder.io.immediate;
118-
memory.writePorts(0).data := registers.io.out_b;
119-
120-
program_pointer := program_pointer + 1.U;
145+
memory.writePorts(0).data := registers.io.out_b(7,0);
146+
memory.writePorts(1).enable := true.B;
147+
memory.writePorts(1).address := registers.io.out_a + decoder.io.immediate + 1.U;
148+
memory.writePorts(1).data := registers.io.out_b(15,8);
149+
memory.writePorts(2).enable := true.B;
150+
memory.writePorts(2).address := registers.io.out_a + decoder.io.immediate + 2.U;
151+
memory.writePorts(2).data := registers.io.out_b(23,16);
152+
memory.writePorts(3).enable := true.B;
153+
memory.writePorts(3).address := registers.io.out_a + decoder.io.immediate + 3.U;
154+
memory.writePorts(3).data := registers.io.out_b(31,16);
155+
156+
program_pointer := program_pointer + 4.U;
121157
stage := 0.U;
122158

123159
printf("[SW] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, registers.io.out_a + decoder.io.immediate);
@@ -129,7 +165,7 @@ class Main() extends Module {
129165
registers.io.write_enable := true.B;
130166
registers.io.in := decoder.io.immediate;
131167

132-
program_pointer := program_pointer + 1.U;
168+
program_pointer := program_pointer + 4.U;
133169
stage := 0.U;
134170

135171
printf("[LUI] Rd: %d Immediate: %b\n", decoder.io.rd, decoder.io.immediate);
@@ -141,7 +177,7 @@ class Main() extends Module {
141177
registers.io.write_enable := true.B;
142178
registers.io.in := program_pointer + decoder.io.immediate;
143179

144-
program_pointer := program_pointer + 1.U;
180+
program_pointer := program_pointer + 4.U;
145181
stage := 0.U;
146182

147183
printf("[AUIPC] Rd: %d Immediate: %b\n", decoder.io.rd, decoder.io.immediate);
@@ -155,7 +191,7 @@ class Main() extends Module {
155191
registers.io.write_enable := true.B;
156192
registers.io.in := registers.io.out_a + decoder.io.immediate;
157193

158-
program_pointer := program_pointer + 1.U;
194+
program_pointer := program_pointer + 4.U;
159195
stage := 0.U;
160196

161197
printf("[ADDI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
@@ -174,7 +210,7 @@ class Main() extends Module {
174210
registers.io.in := 0.U;
175211
}
176212

177-
program_pointer := program_pointer + 1.U;
213+
program_pointer := program_pointer + 4.U;
178214
stage := 0.U;
179215

180216
printf("[SLTI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
@@ -193,7 +229,7 @@ class Main() extends Module {
193229
registers.io.in := 0.U;
194230
}
195231

196-
program_pointer := program_pointer + 1.U;
232+
program_pointer := program_pointer + 4.U;
197233
stage := 0.U;
198234

199235
printf("[SLTIU] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
@@ -207,7 +243,7 @@ class Main() extends Module {
207243
registers.io.write_enable := true.B;
208244
registers.io.in := registers.io.out_a ^ decoder.io.immediate;
209245

210-
program_pointer := program_pointer + 1.U;
246+
program_pointer := program_pointer + 4.U;
211247
stage := 0.U;
212248

213249
printf("[XORI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
@@ -221,7 +257,7 @@ class Main() extends Module {
221257
registers.io.write_enable := true.B;
222258
registers.io.in := registers.io.out_a | decoder.io.immediate;
223259

224-
program_pointer := program_pointer + 1.U;
260+
program_pointer := program_pointer + 4.U;
225261
stage := 0.U;
226262

227263
printf("[ORI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
@@ -235,7 +271,7 @@ class Main() extends Module {
235271
registers.io.write_enable := true.B;
236272
registers.io.in := registers.io.out_a & decoder.io.immediate;
237273

238-
program_pointer := program_pointer + 1.U;
274+
program_pointer := program_pointer + 4.U;
239275
stage := 0.U;
240276

241277
printf("[ANDI] Rs1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
@@ -250,7 +286,7 @@ class Main() extends Module {
250286
registers.io.write_enable := true.B;
251287
registers.io.in := registers.io.out_a + registers.io.out_b;
252288

253-
program_pointer := program_pointer + 1.U;
289+
program_pointer := program_pointer + 4.U;
254290
stage := 0.U;
255291

256292
printf("[ADD] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -265,7 +301,7 @@ class Main() extends Module {
265301
registers.io.write_enable := true.B;
266302
registers.io.in := registers.io.out_a - registers.io.out_b;
267303

268-
program_pointer := program_pointer + 1.U;
304+
program_pointer := program_pointer + 4.U;
269305
stage := 0.U;
270306

271307
printf("[SUB] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -279,7 +315,7 @@ class Main() extends Module {
279315
registers.io.write_enable := true.B;
280316
registers.io.in := registers.io.out_a << decoder.io.immediate(5, 0);
281317

282-
program_pointer := program_pointer + 1.U;
318+
program_pointer := program_pointer + 4.U;
283319
stage := 0.U;
284320

285321
printf("[SLLI] Rs1: %d Rd: %d Shift: %d\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate(5, 0));
@@ -298,7 +334,7 @@ class Main() extends Module {
298334
registers.io.in := registers.io.out_a >> decoder.io.immediate(5, 0);
299335
}
300336

301-
program_pointer := program_pointer + 1.U;
337+
program_pointer := program_pointer + 4.U;
302338
stage := 0.U;
303339

304340
when(decoder.io.immediate(10) === 1.U) { // SRAI
@@ -317,7 +353,7 @@ class Main() extends Module {
317353
registers.io.write_enable := true.B;
318354
registers.io.in := registers.io.out_a << registers.io.out_b(5, 0);
319355

320-
program_pointer := program_pointer + 1.U;
356+
program_pointer := program_pointer + 4.U;
321357
stage := 0.U;
322358

323359
printf("[SLL] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -336,7 +372,7 @@ class Main() extends Module {
336372
registers.io.in := registers.io.out_a >> decoder.io.immediate(5, 0);
337373
}
338374

339-
program_pointer := program_pointer + 1.U;
375+
program_pointer := program_pointer + 4.U;
340376
stage := 0.U;
341377

342378
when(decoder.io.immediate(10) === 1.U) { // SRA
@@ -360,7 +396,7 @@ class Main() extends Module {
360396
registers.io.in := 0.U;
361397
}
362398

363-
program_pointer := program_pointer + 1.U;
399+
program_pointer := program_pointer + 4.U;
364400
stage := 0.U;
365401

366402
printf("[SLT] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -380,7 +416,7 @@ class Main() extends Module {
380416
registers.io.in := 0.U;
381417
}
382418

383-
program_pointer := program_pointer + 1.U;
419+
program_pointer := program_pointer + 4.U;
384420
stage := 0.U;
385421

386422
printf("[SLTU] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -395,7 +431,7 @@ class Main() extends Module {
395431
registers.io.write_enable := true.B;
396432
registers.io.in := registers.io.out_a ^ registers.io.out_b;
397433

398-
program_pointer := program_pointer + 1.U;
434+
program_pointer := program_pointer + 4.U;
399435
stage := 0.U;
400436

401437
printf("[XOR] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -410,7 +446,7 @@ class Main() extends Module {
410446
registers.io.write_enable := true.B;
411447
registers.io.in := registers.io.out_a | registers.io.out_b;
412448

413-
program_pointer := program_pointer + 1.U;
449+
program_pointer := program_pointer + 4.U;
414450
stage := 0.U;
415451

416452
printf("[OR] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -425,7 +461,7 @@ class Main() extends Module {
425461
registers.io.write_enable := true.B;
426462
registers.io.in := registers.io.out_a & registers.io.out_b;
427463

428-
program_pointer := program_pointer + 1.U;
464+
program_pointer := program_pointer + 4.U;
429465
stage := 0.U;
430466

431467
printf("[AND] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
@@ -465,7 +501,7 @@ class Main() extends Module {
465501
when(registers.io.out_a === registers.io.out_b) {
466502
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
467503
}.otherwise {
468-
program_pointer := program_pointer + 1.U;
504+
program_pointer := program_pointer + 4.U;
469505
}
470506

471507
stage := 0.U;
@@ -481,7 +517,7 @@ class Main() extends Module {
481517
when(registers.io.out_a =/= registers.io.out_b) {
482518
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
483519
}.otherwise {
484-
program_pointer := program_pointer + 1.U;
520+
program_pointer := program_pointer + 4.U;
485521
}
486522

487523
stage := 0.U;
@@ -497,7 +533,7 @@ class Main() extends Module {
497533
when(registers.io.out_a.asSInt < registers.io.out_b.asSInt) {
498534
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
499535
}.otherwise {
500-
program_pointer := program_pointer + 1.U;
536+
program_pointer := program_pointer + 4.U;
501537
}
502538

503539
stage := 0.U;
@@ -513,7 +549,7 @@ class Main() extends Module {
513549
when(registers.io.out_a.asSInt >= registers.io.out_b.asSInt) {
514550
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
515551
}.otherwise {
516-
program_pointer := program_pointer + 1.U;
552+
program_pointer := program_pointer + 4.U;
517553
}
518554

519555
stage := 0.U;
@@ -529,7 +565,7 @@ class Main() extends Module {
529565
when(registers.io.out_a < registers.io.out_b) {
530566
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
531567
}.otherwise {
532-
program_pointer := program_pointer + 1.U;
568+
program_pointer := program_pointer + 4.U;
533569
}
534570

535571
stage := 0.U;
@@ -545,7 +581,7 @@ class Main() extends Module {
545581
when(registers.io.out_a >= registers.io.out_b) {
546582
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
547583
}.otherwise {
548-
program_pointer := program_pointer + 1.U;
584+
program_pointer := program_pointer + 4.U;
549585
}
550586

551587
stage := 0.U;
@@ -563,11 +599,11 @@ class Main() extends Module {
563599
is("b010_0000011".U) {
564600
registers.io.write_address := rd_buffer;
565601
registers.io.write_enable := true.B;
566-
registers.io.in := memory.readPorts(1).data;
602+
registers.io.in := memory.readPorts(7).data ## memory.readPorts(6).data ## memory.readPorts(5).data ## memory.readPorts(4).data;
567603

568-
program_pointer := program_pointer + 1.U;
604+
program_pointer := program_pointer + 4.U;
569605

570-
printf("[LW] Rd: %d Data: %b\n", rd_buffer, memory.readPorts(1).data);
606+
printf("[LW] Rd: %d Data: %b\n", rd_buffer, memory.readPorts(7).data ## memory.readPorts(6).data ## memory.readPorts(5).data ## memory.readPorts(4).data);
571607
}
572608
}
573609
}

‎src/test/scala/RISCV/MainSpec.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
1616

1717
dut.io.debug_write.poke(true.B);
1818
dut.io.debug_write_data.poke("b000000000111_00000_000_00010_0010011".U(32.W));
19-
dut.io.debug_write_addressess.poke(1.U);
19+
dut.io.debug_write_addressess.poke(4.U);
2020

2121
dut.clock.step(1);
2222

2323
dut.io.debug_write.poke(true.B);
24-
dut.io.debug_write_data.poke("b0000000_00010_00001_001_00010_1100011".U(32.W));
25-
dut.io.debug_write_addressess.poke(2.U);
24+
dut.io.debug_write_data.poke("b0000000_00010_00001_001_00100_1100011".U(32.W));
25+
dut.io.debug_write_addressess.poke(8.U);
2626

2727
dut.clock.step(1);
2828

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