working fib loop cacluation

Author: outercloudstudio

programs/example.bin

@@ -28,7 +28,7 @@ class Main() extends Module {
 
     val program_pointer = RegInit(0.U(32.W));
 
-    val memory = SRAM(1024, UInt(8.W), 8, 4, 0);
+    val memory = SRAM(512000, UInt(8.W), 8, 4, 0);
 
     // Set up register file
     val registers = Module(new Registers())
@@ -104,11 +104,22 @@ class Main() extends Module {
     when(io.execute) {
         printf("\n");
         printf("Stage: %d\n", stage);
-        printf("Operation: %b\n", decoder.io.operation);
-        printf("Program Pointer: %d\n", program_pointer);
-        printf("Data: %b\n", memory.readPorts(3).data ## memory.readPorts(2).data ## memory.readPorts(1).data ## memory.readPorts(0).data);
-        printf("Register 1: %b\n", registers.io.debug_1);
-        printf("Register 2: %b\n", registers.io.debug_2);
+        
+        when(stage =/= 0.U) {
+            printf("Operation: %b\n", decoder.io.operation);
+            printf("Program Pointer: %d\n", program_pointer);
+            printf("Data: %b\n", memory.readPorts(3).data ## memory.readPorts(2).data ## memory.readPorts(1).data ## memory.readPorts(0).data);
+            printf("Register 1: %b\n", registers.io.debug_1);
+            printf("Register 2: %b\n", registers.io.debug_2);
+            printf("Register 3: %b\n", registers.io.debug_3);
+            printf("Register 4: %b\n", registers.io.debug_4);
+            printf("Register 5: %b\n", registers.io.debug_5);
+            printf("Register 6: %b\n", registers.io.debug_6);
+            printf("Register 7: %b\n", registers.io.debug_7);
+            printf("Register 8: %b\n", registers.io.debug_8);
+            printf("Register 9: %b\n", registers.io.debug_9);
+            printf("Register10: %b\n", registers.io.debug_10);
+        }
 
         stage := stage + 1.U;
 

programs/fib-loop.bin

@@ -37,6 +37,14 @@ class Registers() extends Module {
 
         val debug_1 = Output(UInt(32.W));
         val debug_2 = Output(UInt(32.W));
+        val debug_3 = Output(UInt(32.W));
+        val debug_4 = Output(UInt(32.W));
+        val debug_5 = Output(UInt(32.W));
+        val debug_6 = Output(UInt(32.W));
+        val debug_7 = Output(UInt(32.W));
+        val debug_8 = Output(UInt(32.W));
+        val debug_9 = Output(UInt(32.W));
+        val debug_10 = Output(UInt(32.W));
     })
 
     val regs = RegInit(VecInit(Seq.fill(32.toInt)(0.U(32.W))))
@@ -48,6 +56,15 @@ class Registers() extends Module {
 
     io.debug_1 := regs(1);
     io.debug_2 := regs(2);
+    io.debug_3 := regs(3);
+    io.debug_4 := regs(4);
+    io.debug_5 := regs(5);
+    io.debug_5 := regs(5);
+    io.debug_6 := regs(6);
+    io.debug_7 := regs(7);
+    io.debug_8 := regs(8);
+    io.debug_9 := regs(9);
+    io.debug_10 := regs(10);
 
     // Uncomment to print the register contents every time they are accessed
     //printf("Regs: [%d]=%d, [%d]=%d, WE=%b, WA=%d, IN=%d\n", io.read_address_a, io.out_a, io.read_address_b, io.out_b, io.write_enable, io.write_address, io.in)

programs/fib.bin

@@ -4,42 +4,37 @@ import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.must.Matchers
+import scala.io.Source
+import java.nio.file.{Files, Paths}
+import java.nio.ByteBuffer
 
 class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
   "Main should execute LUI correctly" in {
     simulate(new Main()) { dut =>
-      dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b000000000011_00000_000_00001_0010011".U(32.W));
-      dut.io.debug_write_addressess.poke(0.U);
-
-      dut.clock.step(1);
-
-      dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b000000000111_00000_000_00010_0010011".U(32.W));
-      dut.io.debug_write_addressess.poke(4.U);
-
-      dut.clock.step(1);
-
-      dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b0000000_00010_00001_001_00100_1100011".U(32.W));
-      dut.io.debug_write_addressess.poke(8.U);
-
-      dut.clock.step(1);
+      val bytes = Files.readAllBytes(Paths.get("./programs/fib-loop.bin"))
+      
+      val instructions = bytes.grouped(4).map { instrBytes =>
+        val paddedBytes = instrBytes.padTo(4, 0.toByte)
+        val signedInt = ByteBuffer.wrap(paddedBytes).order(java.nio.ByteOrder.BIG_ENDIAN).getInt()
+        signedInt.toLong & 0xFFFFFFFFL
+      }.toSeq
+
+      dut.io.debug_write.poke(true.B)
+      instructions.zipWithIndex.foreach { case (instr, idx) =>
+        println(s"Instruction: ${instr.toBinaryString.reverse.padTo(32, '0').reverse}")
+        println(s"Address: ${idx * 4}")
+
+        dut.io.debug_write_data.poke(instr.U(32.W))
+        dut.io.debug_write_addressess.poke((idx * 4).U)
+        dut.clock.step(1)
+      }
 
       dut.io.debug_write.poke(false.B);
       dut.io.execute.poke(true.B);
 
       dut.clock.step(1);
 
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
+      dut.clock.step(50);
     }
   }
 }