implement jal

Author: outercloudstudio

documentation/Modules/Hart.md

@@ -39,7 +39,7 @@ Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests
 - [ ] SB
 - [ ] SH
 - [x] SW
-- [ ] JAL
+- [x] JAL
 - [ ] JALR
 - [ ] BEQ
 - [ ] BNE

src/main/scala/RISCV/Decoder.scala

@@ -42,7 +42,7 @@ class Decoder(val width: Int = 32) extends Module {
 		is(0b1110011.U) { format := InstructionFormat.S; } // ecall, ebreak, sret, mret, wfi, sfence.vma | the format for these is not within the standard formats but we can basically achieve the same thing with S type and then using the immediate, rs2, and rs1 to differentiate the calls. Also technically sret, mret, and wfi come from the privelleged spec but we'll just include them here.
 		is(0b0000011.U) { format := InstructionFormat.I; } // lb, lh, lw, lbu, lhu
 		is(0b0100011.U) { format := InstructionFormat.S; } // sb, sh, sw
-		is(0b1101111.U) { format := InstructionFormat.U; } // jal
+		is(0b1101111.U) { format := InstructionFormat.J; } // jal
 		is(0b1100111.U) { format := InstructionFormat.I; } // jalr
 		is(0b1100011.U) { format := InstructionFormat.B; } // beq, bne, blt, bge, bltu, bgeu
 	}

src/main/scala/RISCV/Main.scala

@@ -430,6 +430,18 @@ class Main() extends Module {
 
                     printf("[AND] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
                 }
+
+                // JAL
+                is("b1101111".U) { 
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := program_pointer + 1.U;
+
+                    program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
+                    stage := 0.U;
+
+                    printf("[JAL] Rd: %d Immediate: %b\n", decoder.io.rd, decoder.io.immediate);
+                }
             }
         }
 

src/test/scala/RISCV/MainSpec.scala

@@ -15,29 +15,23 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
       dut.clock.step(1);
 
       dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b0000000_00001_00000_010_01000_0100011".U(32.W));
+      dut.io.debug_write_data.poke("b00000000001000000000_00001_1101111".U(32.W));
       dut.io.debug_write_addressess.poke(1.U);
 
       dut.clock.step(1);
 
       dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b000000001000_00000_010_00010_0000011".U(32.W));
+      dut.io.debug_write_data.poke("b000000000110_00000_000_00010_0010011".U(32.W));
       dut.io.debug_write_addressess.poke(2.U);
 
       dut.clock.step(1);
 
       dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b0100000_00001_00001_101_00010_0010011".U(32.W));
+      dut.io.debug_write_data.poke("b000000000111_00000_000_00010_0010011".U(32.W));
       dut.io.debug_write_addressess.poke(3.U);
 
       dut.clock.step(1);
 
-      dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b0000000_00001_00010_011_00010_0110011".U(32.W));
-      dut.io.debug_write_addressess.poke(4.U);
-
-      dut.clock.step(1);
-
       dut.io.debug_write.poke(false.B);
       dut.io.execute.poke(true.B);
 
@@ -52,8 +46,6 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
       dut.clock.step(1);
       dut.clock.step(1);
       dut.clock.step(1);
-      dut.clock.step(1);
-      dut.clock.step(1);
     }
   }
 }