working sw instruction

Author: outercloudstudio

src/main/scala/RISCV/Decoder.scala

@@ -60,19 +60,19 @@ class Decoder(val width: Int = 32) extends Module {
 		}
 		is(InstructionFormat.S) {
 			io.operation := io.instruction(14,12) ## io.instruction(6,0);
-			io.immediate := io.instruction(31,31) ## 0.U(20.W) ## io.instruction(31,25) ## io.instruction(11,7);
+			io.immediate := Fill(21, io.instruction(31,31)) ## io.instruction(31,25) ## io.instruction(11,7);
 		}
 		is(InstructionFormat.B) {
 			io.operation := io.instruction(14,12) ## io.instruction(6,0);
-			io.immediate := io.instruction(31,31) ## 0.U(19.W) ## io.instruction(7,7) ## io.instruction(31,25) ## io.instruction(11,8) ## 0.U(1.W);
+			io.immediate := Fill(20, io.instruction(31,31)) ## io.instruction(7,7) ## io.instruction(31,25) ## io.instruction(11,8) ## 0.U(1.W);
 		}
 		is(InstructionFormat.U) {
 			io.operation := io.instruction(6,0);
 			io.immediate := io.instruction(31,12) ## 0.U(12.W);
 		}
 		is(InstructionFormat.J) {
 			io.operation := io.instruction(6,0);
-			io.immediate := io.instruction(31,31) ## 0.U(11.W) ## io.instruction(19,12) ## io.instruction(20,20) ## io.instruction(30,21) ## 0.U(1.W);
+			io.immediate := Fill(12, io.instruction(31,31)) ## io.instruction(19,12) ## io.instruction(20,20) ## io.instruction(30,21) ## 0.U(1.W);
 		}
 	}
 }

src/main/scala/RISCV/Main.scala

@@ -76,6 +76,8 @@ class Main() extends Module {
     memory.writePorts(0).data := io.debug_write_data;
 
     val operation_buffer = RegInit(0.U(17.W));
+    val rs1_buffer = RegInit(0.U(5.W));
+    val rs2_buffer = RegInit(0.U(5.W));
     val rd_buffer = RegInit(0.U(5.W));
 
     when(io.execute) {
@@ -85,11 +87,14 @@ class Main() extends Module {
         printf("Program Pointer: %d\n", program_pointer);
         printf("Data: %b\n", memory.readPorts(0).data);
         printf("Register 1: %b\n", regFile.io.debug_1);
+        printf("Register 2: %b\n", regFile.io.debug_2);
 
         stage := stage + 1.U;
 
         when(stage === 1.U) {
             operation_buffer := decoder.io.operation;
+            rs1_buffer := decoder.io.rs1;
+            rs2_buffer := decoder.io.rs2;
             rd_buffer := decoder.io.rd;
 
             switch(decoder.io.operation) {
@@ -102,6 +107,21 @@ class Main() extends Module {
 
                     printf("[LW] Rs1: %d Immediate: %b\n", decoder.io.rs1, regFile.io.out_A + decoder.io.immediate);
                 }
+
+                // SW
+                is("b010_01000_11".U) {
+                    regFile.io.read_addr_A := decoder.io.rs1;
+                    regFile.io.read_addr_B := decoder.io.rs2;
+
+                    memory.writePorts(0).enable := true.B;
+                    memory.writePorts(0).address := regFile.io.out_A + decoder.io.immediate;
+                    memory.writePorts(0).data := regFile.io.out_B;
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+                    
+                    printf("[SW] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, regFile.io.out_A + decoder.io.immediate);
+                }
 
                 // LUI
                 is("b01101_11".U(7.W)) { 

src/main/scala/RISCV/Registers.scala

@@ -34,8 +34,9 @@ class Registers() extends Module {
         val out_A = Output(UInt(32.W))
         val out_B = Output(UInt(32.W))
         val out_C = Output(UInt(32.W)) // Testing output port
-        
-        val debug_1 = Output(UInt(32.W))
+
+        val debug_1 = Output(UInt(32.W));
+        val debug_2 = Output(UInt(32.W));
     })
 
     val regs = RegInit(VecInit(Seq.fill(32.toInt)(0.U(32.W))))
@@ -46,6 +47,7 @@ class Registers() extends Module {
     io.out_C := regs(io.read_addr_C)
 
     io.debug_1 := regs(1);
+    io.debug_2 := regs(2);
 
     // Uncomment to print the register contents every time they are accessed
     //printf("Regs: [%d]=%d, [%d]=%d, WE=%b, WA=%d, IN=%d\n", io.read_addr_A, io.out_A, io.read_addr_B, io.out_B, io.write_enable, io.write_addr, io.in)

src/test/scala/RISCV/MainSpec.scala

@@ -12,32 +12,32 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
       dut.io.debug_write_data.poke("b000000000110_00000_000_00001_0010011".U(32.W));
       dut.io.debug_write_address.poke(0.U);
 
-      dut.clock.step(1)
+      dut.clock.step(1);
 
       dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b000000000110_00001_000_00001_0010011".U(32.W));
+      dut.io.debug_write_data.poke("b0000000_00001_00000_010_01000_0100011".U(32.W));
       dut.io.debug_write_address.poke(1.U);
 
-      dut.clock.step(1)
+      dut.clock.step(1);
 
-      // dut.io.debug_write.poke(true.B);
-      // dut.io.debug_write_data.poke("b000000000000_00000_010_00001_0000011".U(32.W));
-      // dut.io.debug_write_address.poke(1.U);
+      dut.io.debug_write.poke(true.B);
+      dut.io.debug_write_data.poke("b000000001000_00000_010_00010_0000011".U(32.W));
+      dut.io.debug_write_address.poke(2.U);
 
-      // dut.clock.step(1)
+      dut.clock.step(1);
 
       dut.io.debug_write.poke(false.B);
       dut.io.execute.poke(true.B);
 
-      dut.clock.step(1)
-      
-      dut.clock.step(1)
-
-      dut.clock.step(1)
-      
-      dut.clock.step(1)
+      dut.clock.step(1);
 
-      dut.clock.step(1)
+      dut.clock.step(1);
+      dut.clock.step(1);
+      dut.clock.step(1);
+      dut.clock.step(1);
+      dut.clock.step(1);
+      dut.clock.step(1);
+      dut.clock.step(1);
     }
   }
 }