Some cleanup of comments

Author: outercloudstudio

src/main/scala/RISCV/Main.scala

@@ -174,10 +174,6 @@ class Main() extends Module {
     }
 }
 
-/**
-  * Object to generate Verilog/SystemVerilog for the module.
-  * Customize firtoolOpts if needed.
-  */
 object Main extends App {
   ChiselStage.emitSystemVerilogFile(
     new Main(),

src/main/scala/RISCV/PC.scala

@@ -17,10 +17,7 @@ class PC() extends Module {
     io.pc_out := pc_reg
 }
 
-/**
-  * Object to generate Verilog/SystemVerilog for the module.
-  * Customize firtoolOpts if needed.
-  */
+
 object PC extends App {
   ChiselStage.emitSystemVerilogFile(
     new PC(),