Add ALU

Author: outercloudstudio

.gitignore

@@ -319,8 +319,7 @@ dist/*
 target/
 lib_managed/
 src_managed/
-project/boot/
-project/plugins/project/
+project/
 
 # Scala-IDE specific
 .scala_dependencies

generated/ALU.sv

@@ -0,0 +1,17 @@
+// Generated by CIRCT firtool-1.128.0
+module ALU(
+  input         clock,
+                reset,
+                io_add,
+                io_compare,
+  input  [31:0] io_a,
+                io_b,
+  output [31:0] io_output
+);
+
+  assign io_output =
+    io_compare
+      ? {29'h0, io_a > io_b, io_a == io_b, io_a < io_b}
+      : io_add ? io_a + io_b : io_a * io_b;
+endmodule
+

generated/filelist.f

@@ -0,0 +1 @@
+ALU.sv

project/build.properties

@@ -1,3 +1,43 @@
 package RISCV
 
+import chisel3._
+import chisel3.util._
+import _root_.circt.stage.ChiselStage
 
+class ALU(val width: Int = 32) extends Module {
+    val io = IO(new Bundle {
+        val add = Input(Bool());
+        val compare = Input(Bool());
+
+        val a = Input(UInt(width.W));
+        val b = Input(UInt(width.W));
+
+        val output = Output(UInt(width.W));
+    })
+
+    when(io.compare) {
+      val gt = io.a > io.b;
+      val eq = io.a === io.b;
+      val lt = io.a < io.b;
+
+      io.output := Cat(0.U((width - 3).W), gt, eq, lt);
+    }.otherwise {
+        when(io.add) {
+            io.output := io.a + io.b;
+        }.otherwise {
+            io.output := io.a * io.b;
+        }
+    }
+}
+
+object ALU extends App {
+  ChiselStage.emitSystemVerilogFile(
+    new ALU(32),
+    firtoolOpts = Array(
+      "-disable-all-randomization",
+      "-strip-debug-info",
+      "-default-layer-specialization=enable"
+    ),
+    args = Array("--target-dir", "generated")
+  )
+}

project/plugins.sbt

@@ -15,5 +15,5 @@ class Hart(val width: Int = 32) extends Module {
 
     val program_pointer = RegInit(0.U(width.W))
 
-    val registers = Module(new Registers(width, 32));
+    val registers = Module(new Registers());
 }