Fix reading incorrect location from memory

Author: outercloudstudio

src/main/scala/main/Core.scala

@@ -18,8 +18,8 @@ class Core extends Module {
   val dispatcher = Module(new Dispatcher());
   val thread = Module(new Thread());
 
-  memory.io.readPorts(0).enable := 3.U * dispatcher.io.read_requested;
-  memory.io.readPorts(0).address := dispatcher.io.read_program_pointer;
+  memory.io.readPorts(0).enable := dispatcher.io.read_requested;
+  memory.io.readPorts(0).address := 3.U * dispatcher.io.read_program_pointer;
   memory.io.readPorts(1).enable := dispatcher.io.read_requested;
   memory.io.readPorts(1).address := 3.U * dispatcher.io.read_program_pointer + 1.U;
   memory.io.readPorts(2).enable := dispatcher.io.read_requested;

src/main/scala/main/Dispatcher.scala

@@ -50,7 +50,7 @@ class Dispatcher extends Module {
     printf(p"\t[Dispatcher]=====");
     printf(p"\n\t\tRead Complete ${io.read_opcode}");
     printf(p"\n\t\tImmediate Lower ${io.read_immediate_l}");
-    printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}");
+    printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}\n\n");
 
     opcode := Operation.safe(io.read_opcode(6, 3))._1;
 

src/main/scala/main/Thread.scala

@@ -24,7 +24,7 @@ class Thread extends Module {
 
   val register_a = RegInit(2.U(16.W));
   val register_b = RegInit(3.U(16.W));
-  val register_c = RegInit(0.U(16.W));
+  val register_c = RegInit(7.U(16.W));
 
   val alu = Module(new Alu())
   alu.io.execute := false.B;
@@ -99,6 +99,8 @@ class Thread extends Module {
     printf(p"\n\t\ta=${register_a}");
     printf(p"\n\t\tb=${register_b}");
     printf(p"\n\t\tc=${register_c}");
+    printf(p"\n\t\tSrc Register=${io.src_register}");
+    printf(p"\n\t\tDst Register=${io.dst_register}");
     printf(p"\n\n");
   }
 }

src/test/scala/main/CoreTest.scala

@@ -7,10 +7,14 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
     test(new Core) { dut =>
       dut.io.debug_memory_write.poke(true.B);
       dut.io.debug_memory_write_address.poke(0.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00100000.U(8.W));
+      dut.io.debug_memory_write_data.poke(0b00100010.U(8.W));
 
       println("[CoreTest]=====");
       dut.clock.step(1);
+
+      dut.io.debug_memory_write.poke(true.B);
+      dut.io.debug_memory_write_address.poke(3.U(8.W));
+      dut.io.debug_memory_write_data.poke(0b00100001.U(8.W));
 
       println("[CoreTest]=====");
       dut.clock.step(1);
@@ -26,6 +30,21 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
 
       println("[CoreTest]=====");
       dut.clock.step(1);
+
+      println("[CoreTest]=====");
+      dut.clock.step(1);
+
+      println("[CoreTest]=====");
+      dut.clock.step(1);
+
+      println("[CoreTest]=====");
+      dut.clock.step(1);
+
+      println("[CoreTest]=====");
+      dut.clock.step(1);
+
+      println("[CoreTest]=====");
+      dut.clock.step(1);
     }
   }
 }