Implement move immediate op

Author: outercloudstudio

src/main/scala/main/Core.scala

@@ -4,6 +4,8 @@ import _root_.circt.stage.ChiselStage
 
 class Core extends Module {
   val io = IO(new Bundle {
+    val execute = Input(Bool());
+
     val debug_memory_write = Input(Bool());
     val debug_memory_write_address = Input(UInt(8.W));
     val debug_memory_write_data = Input(UInt(8.W));
@@ -29,7 +31,7 @@ class Core extends Module {
   memory.io.writePorts(0).address := io.debug_memory_write_address;
   memory.io.writePorts(0).data := io.debug_memory_write_data;
 
-  dispatcher.io.thread_requesting_opcode := thread.io.idle;
+  dispatcher.io.thread_requesting_opcode := thread.io.idle && io.execute;
   dispatcher.io.thread_program_pointer := thread.io.program_pointer;
 
   val read_ready_delayed = RegNext(dispatcher.io.read_requested, false.B);
@@ -59,8 +61,7 @@ class Core extends Module {
   thread.io.operation := dispatcher.io.opcode;
   thread.io.src_register := dispatcher.io.src_register;
   thread.io.dst_register := dispatcher.io.dst_register;
-  thread.io.immediate_a := 2.U(8.W);
-  thread.io.immediate_b := 3.U(8.W);
+  thread.io.immediate := Cat(dispatcher.io.read_immediate_u, dispatcher.io.read_immediate_l);
 
   io.debug_thread_debug_output := thread.io.debug_output;
 }

src/main/scala/main/Thread.scala

@@ -10,8 +10,7 @@ class Thread extends Module {
     val operation = Input(Operation());
     val src_register = Input(Register());
     val dst_register = Input(Register());
-    val immediate_a = Input(UInt(8.W));
-    val immediate_b = Input(UInt(8.W));
+    val immediate = Input(UInt(16.W));
 
     val program_pointer = Output(UInt(8.W));
     val end_of_program = Output(Bool()); 
@@ -22,9 +21,9 @@ class Thread extends Module {
   val end_of_program = RegInit(false.B);
   val idle = RegInit(true.B);
 
-  val register_a = RegInit(2.U(16.W));
-  val register_b = RegInit(3.U(16.W));
-  val register_c = RegInit(7.U(16.W));
+  val register_a = RegInit(0.U(16.W));
+  val register_b = RegInit(0.U(16.W));
+  val register_c = RegInit(0.U(16.W));
 
   val alu = Module(new Alu())
   alu.io.execute := false.B;
@@ -89,7 +88,17 @@ class Thread extends Module {
     }
 
     when(io.operation === Operation.MoveImmediate) {
-      
+      when(io.dst_register === Register.A) {
+        register_a := io.immediate
+      }
+
+      when(io.dst_register === Register.B) {
+        register_b := io.immediate
+      }
+
+      when(io.dst_register === Register.C) {
+        register_c := io.immediate
+      }
     }
 
     when(io.operation === Operation.MoveRegister) { 

src/test/scala/main/CoreTest.scala

@@ -7,21 +7,27 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
     test(new Core) { dut =>
       dut.io.debug_memory_write.poke(true.B);
       dut.io.debug_memory_write_address.poke(0.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00010010.U(8.W));
+      dut.io.debug_memory_write_data.poke(0b00001010.U(8.W));
 
       println("[CoreTest]=====");
       dut.clock.step(1);
 
       dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(3.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00100010.U(8.W));
+      dut.io.debug_memory_write_address.poke(1.U(8.W));
+      dut.io.debug_memory_write_data.poke(0b01000000.U(8.W));
 
       println("[CoreTest]=====");
       dut.clock.step(1);
 
+      dut.io.debug_memory_write.poke(true.B);
+      dut.io.debug_memory_write_address.poke(2.U(8.W));
+      dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
+
       println("[CoreTest]=====");
       dut.clock.step(1);
 
+      dut.io.execute.poke(true.B);
+
       println("[CoreTest]=====");
       dut.clock.step(1);