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Working memory pipelining
1 parent ed047e5 commit 93e191e

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2 files changed

+53
-16
lines changed

2 files changed

+53
-16
lines changed

src/main/scala/main/Dispatcher.scala

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,6 @@ class Dispatcher extends Module {
2121
val program_pointer = Output(UInt(8.W));
2222
});
2323

24-
io.read_program_pointer := io.thread_program_pointer;
25-
io.read_requested := false.B;
26-
2724
val opcode_loaded = RegInit(false.B);
2825
io.opcode_loaded := opcode_loaded;
2926
val opcode = RegInit(Operation.NoOp);
@@ -35,19 +32,19 @@ class Dispatcher extends Module {
3532
val program_pointer = RegInit(0.U(8.W));
3633
io.program_pointer := program_pointer;
3734

38-
when(io.thread_requesting_opcode) {
39-
printf(p"\t[Dispatcher]=====");
40-
printf(p"\n\t\tMarked read requested!\n\n");
35+
val requested_program_pointer = RegInit(0.U(8.W));
36+
37+
io.read_requested := true.B;
4138

42-
io.read_requested := true.B;
39+
when(io.thread_requesting_opcode) {
40+
io.read_program_pointer := io.thread_program_pointer;
41+
requested_program_pointer := io.thread_program_pointer;
42+
}.otherwise {
43+
io.read_program_pointer := io.thread_program_pointer + 1.U;
44+
requested_program_pointer := io.thread_program_pointer + 1.U;
4345
}
4446

4547
when(io.read_ready) {
46-
printf(p"\t[Dispatcher]=====");
47-
printf(p"\n\t\tRead Complete ${io.read_opcode}");
48-
printf(p"\n\t\tImmediate Lower ${io.read_immediate_l}");
49-
printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}\n\n");
50-
5148
val read_opcode = Operation.safe(io.read_opcode(6, 3))._1;
5249
opcode := read_opcode;
5350
io.opcode := read_opcode;
@@ -105,9 +102,7 @@ class Dispatcher extends Module {
105102
opcode_loaded := true.B;
106103
io.opcode_loaded := true.B;
107104

108-
program_pointer := io.read_program_pointer;
109-
io.program_pointer := io.read_program_pointer;
110-
111-
io.read_requested := false.B;
105+
program_pointer := requested_program_pointer;
106+
io.program_pointer := requested_program_pointer;
112107
}
113108
}

src/test/scala/main/CoreTest.scala

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,48 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
2626
println("[CoreTest]=====");
2727
dut.clock.step(1);
2828

29+
dut.io.debug_memory_write.poke(true.B);
30+
dut.io.debug_memory_write_address.poke(3.U(8.W));
31+
dut.io.debug_memory_write_data.poke(0b00001000.U(8.W));
32+
33+
println("[CoreTest]=====");
34+
dut.clock.step(1);
35+
36+
dut.io.debug_memory_write.poke(true.B);
37+
dut.io.debug_memory_write_address.poke(4.U(8.W));
38+
dut.io.debug_memory_write_data.poke(0b00100010.U(8.W));
39+
40+
println("[CoreTest]=====");
41+
dut.clock.step(1);
42+
43+
dut.io.debug_memory_write.poke(true.B);
44+
dut.io.debug_memory_write_address.poke(5.U(8.W));
45+
dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
46+
47+
println("[CoreTest]=====");
48+
dut.clock.step(1);
49+
50+
dut.io.debug_memory_write.poke(true.B);
51+
dut.io.debug_memory_write_address.poke(6.U(8.W));
52+
dut.io.debug_memory_write_data.poke(0b00100000.U(8.W));
53+
54+
println("[CoreTest]=====");
55+
dut.clock.step(1);
56+
57+
dut.io.debug_memory_write.poke(true.B);
58+
dut.io.debug_memory_write_address.poke(7.U(8.W));
59+
dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
60+
61+
println("[CoreTest]=====");
62+
dut.clock.step(1);
63+
64+
dut.io.debug_memory_write.poke(true.B);
65+
dut.io.debug_memory_write_address.poke(8.U(8.W));
66+
dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
67+
68+
println("[CoreTest]=====");
69+
dut.clock.step(1);
70+
2971
dut.io.execute.poke(true.B);
3072

3173
println("[CoreTest]=====");

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