Loading 24 bits of memory per instruction

Author: outercloudstudio

src/test/scala/main/AluTest.scala src/main/disabled-tests/AluTest.scalasrc/test/scala/main/AluTest.scala renamed to src/main/disabled-tests/AluTest.scala

@@ -18,8 +18,12 @@ class Core extends Module {
   val dispatcher = Module(new Dispatcher());
   val thread = Module(new Thread());
 
-  memory.io.readPorts(0).enable := dispatcher.io.read_requested;
+  memory.io.readPorts(0).enable := 3.U * dispatcher.io.read_requested;
   memory.io.readPorts(0).address := dispatcher.io.read_program_pointer;
+  memory.io.readPorts(1).enable := dispatcher.io.read_requested;
+  memory.io.readPorts(1).address := 3.U * dispatcher.io.read_program_pointer + 1.U;
+  memory.io.readPorts(2).enable := dispatcher.io.read_requested;
+  memory.io.readPorts(2).address := 3.U * dispatcher.io.read_program_pointer + 2.U;
 
   memory.io.writePorts(0).enable := io.debug_memory_write;
   memory.io.writePorts(0).address := io.debug_memory_write_address;
@@ -30,7 +34,9 @@ class Core extends Module {
 
   val read_ready_delayed = RegNext(dispatcher.io.read_requested, false.B);
   dispatcher.io.read_ready := read_ready_delayed;
-  dispatcher.io.read_opcode := Operation.safe(memory.io.readPorts(0).data(3, 0))._1;
+  dispatcher.io.read_opcode := Operation.safe(memory.io.readPorts(0).data(6, 3))._1;
+  dispatcher.io.read_immediate_l := memory.io.readPorts(1).data(7, 0);
+  dispatcher.io.read_immediate_u := memory.io.readPorts(2).data(7, 0);
 
   when(true.B) {
     printf(p"\t[Core]=====");

src/test/scala/main/DispatcherTest.scala …main/disabled-tests/DispatcherTest.scalasrc/test/scala/main/DispatcherTest.scala renamed to src/main/disabled-tests/DispatcherTest.scala src/test/scala/main/DispatcherTest.scala renamed to src/main/disabled-tests/DispatcherTest.scala

@@ -12,6 +12,8 @@ class Dispatcher extends Module {
     val read_program_pointer = Output(UInt(8.W));
     val read_ready = Input(Bool());
     val read_opcode = Input(Operation());
+    val read_immediate_l = Input(UInt(8.W));
+    val read_immediate_u = Input(UInt(8.W));
 
     val opcode_loaded = Output(Bool());
     val opcode = Output(Operation());
@@ -31,15 +33,17 @@ class Dispatcher extends Module {
   io.program_pointer := program_pointer;
 
   when(io.thread_requesting_opcode) {
-    // printf(p"\t[Dispatcher]=====");
-    // printf(p"\n\t\tMarked read requested!\n\n");
+    printf(p"\t[Dispatcher]=====");
+    printf(p"\n\t\tMarked read requested!\n\n");
     read_program_pointer := io.thread_program_pointer;
     read_requested := true.B;
   }
 
   when(io.read_ready) {
     printf(p"\t[Dispatcher]=====");
-    printf(p"\n\t\tRead Complete ${io.read_opcode}\n\n");
+    printf(p"\n\t\tRead Complete ${io.read_opcode}");
+    printf(p"\n\t\tImmediate Lower ${io.read_immediate_l}");
+    printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}\n\n");
     opcode := io.read_opcode;
     opcode_loaded := true.B;
     program_pointer := io.read_program_pointer;

src/test/scala/main/LsuTest.scala src/main/disabled-tests/LsuTest.scalasrc/test/scala/main/LsuTest.scala renamed to src/main/disabled-tests/LsuTest.scala

@@ -3,10 +3,13 @@ import chisel3.util._
 import _root_.circt.stage.ChiselStage
 
 class Memory extends Module {
-  val io = IO(new SRAMInterface(1024, UInt(8.W), 1, 1, 0));
+  val io = IO(new SRAMInterface(1024, UInt(8.W), 3, 1, 0));
 
-  val memory = SRAM(1024, UInt(8.W), 1, 1, 0);
+  val memory = SRAM(1024, UInt(8.W), 3, 1, 0);
 
   io.readPorts(0) <> memory.readPorts(0);
+  io.readPorts(1) <> memory.readPorts(1);
+  io.readPorts(2) <> memory.readPorts(2);
+  
   io.writePorts(0) <> memory.writePorts(0);
 }

…test/scala/main/ProgramCounterTest.scala …/disabled-tests/ProgramCounterTest.scalasrc/test/scala/main/ProgramCounterTest.scala renamed to src/main/disabled-tests/ProgramCounterTest.scala src/test/scala/main/ProgramCounterTest.scala renamed to src/main/disabled-tests/ProgramCounterTest.scala

@@ -3,5 +3,5 @@ import chisel3.util._
 import _root_.circt.stage.ChiselStage
 
 object Operation extends ChiselEnum {
-  val NoOp, Add, Sub, Mul, Div, JumpE, JumpNE, Compare, End, Load, Write = Value
+  val NoOp, MoveImmediate, MoveRegister, Load, Add, Sub, Mul, Div, JumpE, JumpNE, Compare, End, Write = Value
 }

src/test/scala/main/ThreadTest.scala src/main/disabled-tests/ThreadTest.scalasrc/test/scala/main/ThreadTest.scala renamed to src/main/disabled-tests/ThreadTest.scala

@@ -20,6 +20,9 @@ class Thread extends Module {
   val end_of_program = RegInit(false.B);
   val idle = RegInit(true.B);
 
+  val register_a = RegInit(0.U(16.W));
+  val register_b = RegInit(0.U(16.W));
+
   val alu = Module(new Alu())
   alu.io.execute := false.B;
   alu.io.operation := Operation.NoOp;