feat other

Author: MKMonkeyCat

lib/adder/full_adder/README.md

@@ -7,17 +7,23 @@ full_adder(input A, B, Ci, output Co, S)
 ![RTL_View](./assets/RTL_view.png)
 ![Symbol](./assets/Symbol.png)
 
-> Equivalent module:
+### Other logic full adder
 
 ```v
-module full_adder(input A, B, Ci, output Co, S);
+module s_full_adder(input A, B, Ci, output Co, S);
   assign S = A ^ B ^ Ci;
   assign Co = (A & B) | ((A ^ B) & Ci);
 endmodule
 ```
 
+![S-Full adder](assets/s_RTL_view.png)
+
+> Verilog special syntax
+
 ```v
-module full_adder(input A, B, Ci, output Co, S);
+module v_full_adder(input A, B, Ci, output Co, S);
   assign {Co, S} = A + B + Ci;
 endmodule
 ```
+
+![V-Full adder](assets/v_RTL_view.png)

lib/adder/full_adder/assets/s_RTL_view.png

@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors.  Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+  (rect 16 16 112 112)
+  (text "s_full_adder" (rect 5 0 29 12)(font "Arial" ))
+  (text "inst" (rect 8 80 25 92)(font "Arial" ))
+  (port
+    (pt 0 32)
+    (input)
+    (text "A" (rect 0 0 7 12)(font "Arial" ))
+    (text "A" (rect 21 27 28 39)(font "Arial" ))
+    (line (pt 0 32)(pt 16 32)(line_width 1))
+  )
+  (port
+    (pt 0 48)
+    (input)
+    (text "B" (rect 0 0 7 12)(font "Arial" ))
+    (text "B" (rect 21 43 28 55)(font "Arial" ))
+    (line (pt 0 48)(pt 16 48)(line_width 1))
+  )
+  (port
+    (pt 0 64)
+    (input)
+    (text "Ci" (rect 0 0 10 12)(font "Arial" ))
+    (text "Ci" (rect 21 59 31 71)(font "Arial" ))
+    (line (pt 0 64)(pt 16 64)(line_width 1))
+  )
+  (port
+    (pt 96 32)
+    (output)
+    (text "Co" (rect 0 0 14 12)(font "Arial" ))
+    (text "Co" (rect 61 27 75 39)(font "Arial" ))
+    (line (pt 96 32)(pt 80 32)(line_width 1))
+  )
+  (port
+    (pt 96 48)
+    (output)
+    (text "S" (rect 0 0 7 12)(font "Arial" ))
+    (text "S" (rect 68 43 75 55)(font "Arial" ))
+    (line (pt 96 48)(pt 80 48)(line_width 1))
+  )
+  (drawing
+    (rectangle (rect 16 16 80 80)(line_width 1))
+  )
+)

lib/adder/full_adder/assets/v_RTL_view.png

@@ -1,4 +1,4 @@
 module s_full_adder(input A, B, Ci, output Co, S);
   assign S = A ^ B ^ Ci;
-  assign Co = (A & B) + (B & Ci) + (A & Ci);
+  assign Co = (A & B) | (B & Ci) | (A & Ci);
 endmodule

lib/adder/full_adder/s_full_adder.bsf

@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors.  Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+  (rect 16 16 112 112)
+  (text "v_full_adder" (rect 5 0 29 12)(font "Arial" ))
+  (text "inst" (rect 8 80 25 92)(font "Arial" ))
+  (port
+    (pt 0 32)
+    (input)
+    (text "A" (rect 0 0 7 12)(font "Arial" ))
+    (text "A" (rect 21 27 28 39)(font "Arial" ))
+    (line (pt 0 32)(pt 16 32)(line_width 1))
+  )
+  (port
+    (pt 0 48)
+    (input)
+    (text "B" (rect 0 0 7 12)(font "Arial" ))
+    (text "B" (rect 21 43 28 55)(font "Arial" ))
+    (line (pt 0 48)(pt 16 48)(line_width 1))
+  )
+  (port
+    (pt 0 64)
+    (input)
+    (text "Ci" (rect 0 0 10 12)(font "Arial" ))
+    (text "Ci" (rect 21 59 31 71)(font "Arial" ))
+    (line (pt 0 64)(pt 16 64)(line_width 1))
+  )
+  (port
+    (pt 96 32)
+    (output)
+    (text "Co" (rect 0 0 14 12)(font "Arial" ))
+    (text "Co" (rect 61 27 75 39)(font "Arial" ))
+    (line (pt 96 32)(pt 80 32)(line_width 1))
+  )
+  (port
+    (pt 96 48)
+    (output)
+    (text "S" (rect 0 0 7 12)(font "Arial" ))
+    (text "S" (rect 68 43 75 55)(font "Arial" ))
+    (line (pt 96 48)(pt 80 48)(line_width 1))
+  )
+  (drawing
+    (rectangle (rect 16 16 80 80)(line_width 1))
+  )
+)

lib/adder/full_adder/s_full_adder.v

@@ -0,0 +1,3 @@
+module v_full_adder(input A, B, Ci, output Co, S);
+  assign {Co, S} = A + B + Ci;
+endmodule

lib/adder/full_adder/v_full_adder.bsf

@@ -1,5 +1,10 @@
 # verilog-library
 
+## Naming conventions
+
+1. `s_`: Less Clock version
+2. `v_`: Verilog special syntax
+
 [TOC]
 
 {CONTENT}