1010]>
1111#compilation = #iree_codegen.compilation_info <lowering_config = #config , translation_info = #translation >
1212module {
13- func.func @preset_config () attributes {hal.executable.target = #executable_target_system_elf_x86_64_ } {
13+ func.func @preset_config_0 () attributes {hal.executable.target = #executable_target_system_elf_x86_64_ } {
14+ %cst = arith.constant 0.000000e+00 : f32
15+ %0 = hal.interface.binding.subspan layout (#pipeline_layout ) binding (0 ) : !iree_tensor_ext.dispatch.tensor <readonly :tensor <128 x256 xf32 >>
16+ %1 = hal.interface.binding.subspan layout (#pipeline_layout ) binding (1 ) : !iree_tensor_ext.dispatch.tensor <readonly :tensor <256 x512 xf32 >>
17+ %2 = hal.interface.binding.subspan layout (#pipeline_layout ) binding (2 ) : !iree_tensor_ext.dispatch.tensor <writeonly :tensor <128 x512 xf32 >>
18+ %3 = iree_tensor_ext.dispatch.tensor.load %0 , offsets = [0 , 0 ], sizes = [128 , 256 ], strides = [1 , 1 ] : !iree_tensor_ext.dispatch.tensor <readonly :tensor <128 x256 xf32 >> -> tensor <128 x256 xf32 >
19+ %4 = iree_tensor_ext.dispatch.tensor.load %1 , offsets = [0 , 0 ], sizes = [256 , 512 ], strides = [1 , 1 ] : !iree_tensor_ext.dispatch.tensor <readonly :tensor <256 x512 xf32 >> -> tensor <256 x512 xf32 >
20+ %5 = tensor.empty () : tensor <128 x512 xf32 >
21+ %6 = linalg.fill ins (%cst : f32 ) outs (%5 : tensor <128 x512 xf32 >) -> tensor <128 x512 xf32 >
22+ %7 = linalg.matmul {compilation_info = #compilation } ins (%3 , %4 : tensor <128 x256 xf32 >, tensor <256 x512 xf32 >) outs (%6 : tensor <128 x512 xf32 >) -> tensor <128 x512 xf32 >
23+ iree_tensor_ext.dispatch.tensor.store %7 , %2 , offsets = [0 , 0 ], sizes = [128 , 512 ], strides = [1 , 1 ] : tensor <128 x512 xf32 > -> !iree_tensor_ext.dispatch.tensor <writeonly :tensor <128 x512 xf32 >>
24+ return
25+ }
26+ func.func @preset_config_1 () attributes {hal.executable.target = #executable_target_system_elf_x86_64_ } {
1427 %cst = arith.constant 0.000000e+00 : f32
1528 %0 = hal.interface.binding.subspan layout (#pipeline_layout ) binding (0 ) : !iree_tensor_ext.dispatch.tensor <readonly :tensor <128 x256 xf32 >>
1629 %1 = hal.interface.binding.subspan layout (#pipeline_layout ) binding (1 ) : !iree_tensor_ext.dispatch.tensor <readonly :tensor <256 x512 xf32 >>
@@ -27,7 +40,11 @@ module {
2740
2841// CHECK-DAG: #[[CONFIG:.+]] = #iree_codegen.lowering_config<tile_sizes = {{\[}}[64, 64, 0], [32, 32, 0], [0, 0, 32], [0, 0, 0]]>
2942// CHECK-DAG: #[[TRANSLATION:.+]] = #iree_codegen.translation_info<pipeline = CPUDoubleTilingExpert>
30- // CHECK: func.func @preset_config()
43+ // CHECK: func.func @preset_config_0()
44+ // CHECK-SAME: translation_info = #[[TRANSLATION]]
45+ // CHECK: linalg.matmul
46+ // CHECK-SAME: lowering_config = #[[CONFIG]]
47+ // CHECK: func.func @preset_config_1()
3148// CHECK-SAME: translation_info = #[[TRANSLATION]]
3249// CHECK: linalg.matmul
3350// CHECK-SAME: lowering_config = #[[CONFIG]]
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