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## New changes - We're starting to pick up TOSA dialect v1.0 changes llvm/llvm-project@360a03c and llvm/llvm-project@c1d01b2 . These are breaking changes so existing TOSA `.mlir[bc]` files may not work with new compiler versions. These changes will also be propagating to framework exporters/importers like TensorFlow over time, so more breaks are expected. The `iree-import-tflite` tool now reports a warning if a known-incompatible version of tensorflow is installed. ## Reverts RISC-V backend - llvm/llvm-project@169c32e Python related changes - llvm/llvm-project@5cd4274 - llvm/llvm-project@08e2c15 - llvm/llvm-project@b56d1ec - llvm/llvm-project@a0f5bbc NVPTX changes - llvm/llvm-project@29b5c18 - llvm/llvm-project@e7a83fc ## Updates to Torch-MLIR - Fix Conv2D create methods https://github.com/iree-org/torch-mlir/tree/integrate/20250112 (to be upstream to Torch-MLIR) --------- Signed-off-by: MaheshRavishankar <[email protected]> Signed-off-by: Krzysztof Drewniak <[email protected]> Signed-off-by: Scott Todd <[email protected]> Co-authored-by: Scott Todd <[email protected]> Co-authored-by: Krzysztof Drewniak <[email protected]>
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14 files changed

+45
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‎compiler/src/iree/compiler/Codegen/Interfaces/BUILD.bazel‎

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@@ -62,6 +62,7 @@ iree_compiler_cc_library(
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"@llvm-project//mlir:AMDGPUDialect",
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"@llvm-project//mlir:ArithValueBoundsOpInterfaceImpl",
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"@llvm-project//mlir:BufferizationTransformOps",
65+
"@llvm-project//mlir:GPUDialect",
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"@llvm-project//mlir:GPUTransformOps",
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"@llvm-project//mlir:LinalgDialect",
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"@llvm-project//mlir:LinalgTransformOps",

‎compiler/src/iree/compiler/Codegen/Interfaces/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ iree_cc_library(
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MLIRAffineTransformOps
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MLIRArithValueBoundsOpInterfaceImpl
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MLIRBufferizationTransformOps
31+
MLIRGPUDialect
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MLIRGPUTransformOps
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MLIRIR
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MLIRLinalgDialect

‎compiler/src/iree/compiler/Codegen/Interfaces/Interfaces.cpp‎

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@@ -23,6 +23,7 @@
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#include "mlir/Dialect/Affine/TransformOps/AffineTransformOps.h"
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#include "mlir/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.h"
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#include "mlir/Dialect/Bufferization/TransformOps/BufferizationTransformOps.h"
26+
#include "mlir/Dialect/GPU/IR/ValueBoundsOpInterfaceImpl.h"
2627
#include "mlir/Dialect/GPU/TransformOps/GPUTransformOps.h"
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#include "mlir/Dialect/Linalg/IR/ValueBoundsOpInterfaceImpl.h"
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#include "mlir/Dialect/Linalg/TransformOps/DialectExtension.h"
@@ -64,6 +65,7 @@ void registerCodegenInterfaces(DialectRegistry &registry) {
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arith::registerValueBoundsOpInterfaceExternalModels(registry);
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bufferization::registerTransformDialectExtension(registry);
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gpu::registerTransformDialectExtension(registry);
68+
gpu::registerValueBoundsOpInterfaceExternalModels(registry);
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linalg::registerTransformDialectExtension(registry);
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linalg::registerValueBoundsOpInterfaceExternalModels(registry);
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linalg::registerSubsetOpInterfaceExternalModels(registry);

‎compiler/src/iree/compiler/Codegen/SPIRV/test/pipeline_matvec.mlir‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -76,18 +76,18 @@ hal.executable @i4_dequant_unit_matmul_f16 {
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// CHECK-DAG: %[[CSTVEC4XI32_255:.+]] = spirv.Constant dense<255> : vector<4xi32>
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// CHECK-DAG: %[[CSTVEC4XI32_0:.+]] = spirv.Constant dense<0> : vector<4xi32>
79-
// CHECK-DAG: %[[CSTVEC2XI32_4:.+]] = spirv.Constant dense<4> : vector<2xi32>
80-
// CHECK-DAG: %[[CSTVEC2XI32_15:.+]] = spirv.Constant dense<15> : vector<2xi32>
79+
// CHECK-DAG: %[[CSTVEC4XI32_0_4:.+]] = spirv.Constant dense<[0, 4, 0, 4]> : vector<4xi32>
80+
// CHECK-DAG: %[[CSTVEC4XI32_15__16:.+]] = spirv.Constant dense<[15, -16, 15, -16]> : vector<4xi32>
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8282
// CHECK: spirv.mlir.loop
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// Load the quantized weight and get 8xi4 out of it.
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// CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %{{.+}} : vector<4xi32>
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// CHECK: %[[SHUF01:.+]] = spirv.VectorShuffle [0 : i32, 1 : i32] %[[LOAD]], %[[LOAD]] : vector<4xi32>, vector<4xi32> -> vector<2xi32>
87-
// CHECK: %[[LOW4:.+]] = spirv.BitwiseAnd %[[SHUF01]], %[[CSTVEC2XI32_15]] : vector<2xi32>
88-
// CHECK: %[[HIGH4:.+]] = spirv.ShiftRightLogical %[[SHUF01]], %[[CSTVEC2XI32_4]] : vector<2xi32>, vector<2xi32>
89-
// CHECK: %[[LOW4HIGH4:.+]] = spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32] %[[LOW4]], %[[HIGH4]] : vector<2xi32>, {{.*}} -> vector<4xi32>
90-
// CHECK: %[[LOW4HIGH4_ZEROUPPER:.+]] = spirv.BitwiseAnd %[[LOW4HIGH4]], %[[CSTVEC4XI32_255]] : vector<4xi32>
87+
// CHECK: %[[SHUF0011:.+]] = spirv.VectorShuffle [0 : i32, 0 : i32, 1 : i32, 1 : i32] %[[SHUF01]], %[[SHUF01]] : vector<2xi32>, vector<2xi32> -> vector<4xi32>
88+
// CHECK: %[[MASKED:.+]] = spirv.BitwiseAnd %[[SHUF0011]], %[[CSTVEC4XI32_15__16]] : vector<4xi32>
89+
// CHECK: %[[SHIFTED:.+]] = spirv.ShiftRightLogical %[[MASKED]], %[[CSTVEC4XI32_0_4]] : vector<4xi32>, vector<4xi32>
90+
// CHECK: %[[LOW4HIGH4_ZEROUPPER:.+]] = spirv.BitwiseAnd %[[SHIFTED]], %[[CSTVEC4XI32_255]] : vector<4xi32>
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// CHECK: %[[SHUF23:.+]] = spirv.VectorShuffle [2 : i32, 3 : i32] %[[LOAD:.+]], %[[LOAD:.+]] : vector<4xi32>, vector<4xi32> -> vector<2xi32>
9393

@@ -186,8 +186,8 @@ hal.executable @i4_dequant_matvec_f16_subgroup_64 {
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// CHECK-DAG: %[[C0:.+]] = spirv.Constant 0 : i32
187187
// CHECK-DAG: %[[CSTVEC4XF16_1:.+]] = spirv.Constant dense<1.000000e+00> : vector<4xf16>
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// CHECK-DAG: %[[CSTVEC4XI32_255:.+]] = spirv.Constant dense<255> : vector<4xi32>
189-
// CHECK-DAG: %[[CSTVEC2XI32_4:.+]] = spirv.Constant dense<4> : vector<2xi32>
190-
// CHECK-DAG: %[[CSTVEC2XI32_15:.+]] = spirv.Constant dense<15> : vector<2xi32>
189+
// CHECK-DAG: %[[CSTVEC2XI32_1:.+]] = spirv.Constant dense<[0, 4, 0, 4]> : vector<4xi32>
190+
// CHECK-DAG: %[[CSTVEC2XI32_2:.+]] = spirv.Constant dense<[15, -16, 15, -16]> : vector<4xi32>
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192192
// CHECK: %[[WIDX:.+]] = spirv.CompositeExtract %{{.*}}[0 : i32] : vector<3xi32>
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// CHECK: %[[PCPTR:.+]] = spirv.AccessChain %{{.*}}[{{.*}}, %[[C0]]] : !spirv.ptr<!spirv.struct<(!spirv.array<5 x i32, stride=4> [0])>, PushConstant>, i32, i32
@@ -209,8 +209,7 @@ hal.executable @i4_dequant_matvec_f16_subgroup_64 {
209209
// CHECK: %[[ACCESS:.+]] = spirv.AccessChain %[[RADDR]][{{.*}}, %[[OFFSET]]] : !spirv.ptr<!spirv.struct<(!spirv.rtarray<i32, stride=4> [0])>, StorageBuffer>, i32, i32
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// CHECK: spirv.Load "StorageBuffer" %[[ACCESS]] : i32
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212-
// CHECK: spirv.ShiftRightLogical %{{.*}}, %[[CSTVEC2XI32_4]] : vector<2xi32>, vector<2xi32>
213-
// CHECK: spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32] %{{.*}} : vector<2xi32>, vector<2xi32> -> vector<4xi32>
212+
// CHECK: spirv.ShiftRightLogical %{{.*}}, %[[CSTVEC2XI32_1]] : vector<4xi32>, vector<4xi32>
214213
// CHECK: spirv.BitwiseAnd %{{.*}}, %[[CSTVEC4XI32_255]] : vector<4xi32>
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// CHECK: spirv.ConvertUToF %{{.+}} : vector<4xi32> to vector<4xf16>

‎compiler/src/iree/compiler/Codegen/SPIRV/test/pipeline_sub_byte_dequant.mlir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,13 +44,13 @@ hal.executable @i4_dequant {
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4545
// CHECK-LABEL: spirv.func @i4_dequant()
4646

47-
// CHECK: spirv.VectorShuffle [0 : i32, 1 : i32] {{.*}} : vector<4xi32>, vector<4xi32> -> vector<2xi32>
48-
// CHECK: spirv.BitwiseAnd
49-
// CHECK: spirv.ShiftRightLogical
50-
// CHECK: spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32]
51-
// CHECK: spirv.BitwiseAnd
47+
// CHECK: %[[BYTE1:.+]] = spirv.VectorShuffle [0 : i32, 1 : i32] {{.*}} : vector<4xi32>, vector<4xi32> -> vector<2xi32>
48+
// CHECK: %[[COPIED:.+]] = spirv.VectorShuffle [0 : i32, 0 : i32, 1 : i32, 1 : i32] %[[BYTE1]], %[[BYTE1]] : vector<2xi32>, vector<2xi32> -> vector<4xi32>
49+
// CHECK: %[[MASKED:.+]] = spirv.BitwiseAnd %[[COPIED]]
50+
// CHECK: %[[SHIFTED:.+]] = spirv.ShiftRightLogical %[[MASKED]]
51+
// CHECK: %[[ZEROUPPER:.+]] = spirv.BitwiseAnd %[[SHIFTED]]
5252
// CHECK: spirv.VectorShuffle [2 : i32, 3 : i32] {{.*}} : vector<4xi32>, vector<4xi32> -> vector<2xi32>
53-
// CHECK-COUNT-3: spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32]
53+
// CHECK-COUNT-3: spirv.VectorShuffle [0 : i32, 0 : i32, 1 : i32, 1 : i32]
5454

5555
// CHECK-COUNT-4: spirv.ConvertUToF {{.+}} : vector<4xi32> to vector<4xf32>
5656
// CHECK-COUNT-4: spirv.FSub

‎compiler/src/iree/compiler/ExternalInterfaces/BUILD.bazel‎

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@@ -37,6 +37,7 @@ iree_compiler_cc_library(
3737
"//compiler/src/iree/compiler/Dialect/Stream/IR",
3838
"//compiler/src/iree/compiler/Dialect/Util/IR",
3939
"@llvm-project//mlir:ArithDialect",
40+
"@llvm-project//mlir:GPUDialect",
4041
"@llvm-project//mlir:IR",
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"@llvm-project//mlir:LinalgDialect",
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"@llvm-project//mlir:LinalgOpsIncGen",

‎compiler/src/iree/compiler/ExternalInterfaces/CMakeLists.txt‎

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@@ -27,6 +27,7 @@ iree_cc_library(
2727
"UtilExternalModels.cpp"
2828
DEPS
2929
MLIRArithDialect
30+
MLIRGPUDialect
3031
MLIRIR
3132
MLIRLinalgDialect
3233
MLIRLinalgOpsIncGenLib

‎integrations/tensorflow/python_projects/iree_tflite/iree/tools/tflite/scripts/iree_import_tflite/__main__.py‎

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@@ -51,6 +51,19 @@ def main():
5151
if args.output_format != "mlir-bytecode":
5252
logging.warning("output-format option is deprecated, emitting MLIR bytecode")
5353

54+
# Log compatibility warnings for some known issues.
55+
try:
56+
from packaging import version
57+
from tensorflow import __version__ as tf_version
58+
59+
# https://discourse.llvm.org/t/rfc-tosa-dialect-increment-to-v1-0/83708
60+
if version.parse(tf_version) <= version.parse("2.18.0"):
61+
logging.warning(
62+
f"Found tensorflow version {tf_version}. Versions of tensorflow<=2.18.0 have known compatibility issues with TOSA v1.0. Consider using a newer tensorflow version or iree-base-compiler<=3.1.0"
63+
)
64+
except:
65+
pass
66+
5467
tflite_to_tosa(
5568
flatbuffer=args.flatbuffer,
5669
bytecode=args.output_path,

‎integrations/tensorflow/test/iree_tfl_tests/gpt2.run‎

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@@ -1 +1,2 @@
11
# RUN: %PYTHON -m iree_tfl_tests.gpt2_test --artifacts_dir=%t
2+
# XFAIL: *

‎integrations/tensorflow/test/iree_tfl_tests/person_detect.run‎

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@@ -1 +1,2 @@
11
# RUN: %PYTHON -m iree_tfl_tests.person_detect_test --artifacts_dir=%t
2+
# XFAIL: *

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