@@ -326,6 +326,12 @@ void VulkanChunker::addBlock(BlockRenderDataId blockRenderDataId, Position posit
326326 (orientation * blockRenderData->size ).free ()
327327 )
328328 );
329+ if (blockRenderData->blockStatePortPosition ) {
330+ logicGroup.getBlockStatePortMapping ().try_emplace (position + orientation.transformVectorWithArea (
331+ blockRenderData->blockStatePortPosition .value (),
332+ blockRenderData->size
333+ ), position);
334+ }
329335 if (newGroup) {
330336 for (auto chunkPosIter = getChunk (position).iterTo (getChunk (position + (orientation * blockRenderData->size ).getLargestVectorInArea ())); chunkPosIter;
331337 ++chunkPosIter) {
@@ -346,6 +352,13 @@ void VulkanChunker::removeBlock(Position position) {
346352 for (LogicGroup* logicGroup : groupsAtChunkIter->second ) {
347353 auto blockIter = logicGroup->getRenderedBlocks ().find (position);
348354 if (blockIter == logicGroup->getRenderedBlocks ().end ()) continue ;
355+ const BlockRenderDataManager::BlockRenderData* blockRenderData = MainRenderer::get ().getBlockRenderDataManager ().getBlockRenderData (blockIter->second .blockRenderDataId );
356+ if (blockRenderData->blockStatePortPosition ) {
357+ logicGroup->getBlockStatePortMapping ().erase (position + blockIter->second .orientation .transformVectorWithArea (
358+ blockRenderData->blockStatePortPosition .value (),
359+ blockRenderData->size
360+ ));
361+ }
349362 logicGroup->getRenderedBlocks ().erase (blockIter);
350363 logicGroupsToUpdate.insert (logicGroup);
351364 return ;
@@ -456,62 +469,51 @@ void VulkanChunker::updateSimulatorIds(const std::vector<SimulatorMappingUpdate>
456469 for (const SimulatorMappingUpdate& simulatorMappingUpdate : simulatorMappingUpdates) {
457470 const std::variant<simulator_id_t , std::vector<simulator_id_t >>& simIds = simulatorMappingUpdate.simulatorIds ;
458471
459- if (simulatorMappingUpdate.type == SimulatorMappingUpdateType::BLOCK) {
460- simulator_id_t simulatorId = simulator_id_t (0 );
472+ Position chunkPos = getChunk (simulatorMappingUpdate.portPosition );
473+ auto groupsAtChunkIter = chunkToGroups.find (chunkPos);
474+ if (groupsAtChunkIter == chunkToGroups.end ()) {
475+ continue ;
476+ }
477+ for (LogicGroup* logicGroup : groupsAtChunkIter->second ) {
478+ std::optional<std::shared_ptr<VulkanLogicAllocation>> vulkanLogicAllocation = logicGroup->getAllocation ();
479+ if (!vulkanLogicAllocation) continue ;
480+ auto blockPosIter = logicGroup->getBlockStatePortMapping ().find (simulatorMappingUpdate.portPosition );
481+ if (blockPosIter == logicGroup->getBlockStatePortMapping ().end ()) continue ;
482+ auto iter = vulkanLogicAllocation.value ()->getBlockStateIndex ().find (blockPosIter->second );
483+ if (iter == vulkanLogicAllocation.value ()->getBlockStateIndex ().end ()) continue ;
461484 if (std::holds_alternative<std::vector<simulator_id_t >>(simIds)) {
462- const std::vector<simulator_id_t >& vec = std::get<std::vector<simulator_id_t >>(simIds);
463- if (!vec.empty ()) {
464- simulatorId = vec[0 ];
465- }
485+ vulkanLogicAllocation.value ()->getStateSimulatorIds ()[iter->second ] = 0 ;
466486 } else {
467- simulatorId = std::get<simulator_id_t >(simIds);
487+ vulkanLogicAllocation. value ()-> getStateSimulatorIds ()[iter-> second ] = std::get<simulator_id_t >(simIds);
468488 }
489+ break ;
490+ }
491+ for (LogicGroup* logicGroup : groupsAtChunkIter->second ) {
492+ std::optional<std::shared_ptr<VulkanLogicAllocation>> vulkanLogicAllocation = logicGroup->getAllocation ();
493+ if (!vulkanLogicAllocation) continue ;
494+ auto portStateIter = vulkanLogicAllocation.value ()->getPortStateIndex ().find (simulatorMappingUpdate.portPosition );
495+ if (portStateIter == vulkanLogicAllocation.value ()->getPortStateIndex ().end ()) continue ;
469496
470- Position chunkPos = getChunk (simulatorMappingUpdate.portPosition );
471- auto groupsAtChunkIter = chunkToGroups.find (chunkPos);
472- if (groupsAtChunkIter == chunkToGroups.end ()) {
473- continue ;
474- }
475- for (LogicGroup* logicGroup : groupsAtChunkIter->second ) {
476- std::optional<std::shared_ptr<VulkanLogicAllocation>> vulkanLogicAllocation = logicGroup->getAllocation ();
477- if (!vulkanLogicAllocation) continue ;
478- auto iter = vulkanLogicAllocation.value ()->getBlockStateIndex ().find (simulatorMappingUpdate.portPosition );
479- if (iter == vulkanLogicAllocation.value ()->getBlockStateIndex ().end ()) continue ;
480- vulkanLogicAllocation.value ()->getStateSimulatorIds ()[iter->second ] = simulatorId;
481- }
482- } else {
483- Position chunkPos = getChunk (simulatorMappingUpdate.portPosition );
484- auto groupsAtChunkIter = chunkToGroups.find (chunkPos);
485- if (groupsAtChunkIter == chunkToGroups.end ()) {
486- continue ;
487- }
488- for (LogicGroup* logicGroup : groupsAtChunkIter->second ) {
489- std::optional<std::shared_ptr<VulkanLogicAllocation>> vulkanLogicAllocation = logicGroup->getAllocation ();
490- if (!vulkanLogicAllocation) continue ;
491- auto portStateIter = vulkanLogicAllocation.value ()->getPortStateIndex ().find (simulatorMappingUpdate.portPosition );
492- if (portStateIter == vulkanLogicAllocation.value ()->getPortStateIndex ().end ()) continue ;
493-
494- const PortStateRange& range = portStateIter->second ;
495- if (!range.isValid ()) continue ;
496-
497- std::vector<simulator_id_t >& chunkStateSimulatorIds = vulkanLogicAllocation.value ()->getStateSimulatorIds ();
498- if (std::holds_alternative<std::vector<simulator_id_t >>(simIds)) {
499- const std::vector<simulator_id_t >& wireSimIds = std::get<std::vector<simulator_id_t >>(simIds);
500- uint32_t laneCount = wireSimIds.size ();
501- if (laneCount != range.laneCount ) {
502- logicGroupsToUpdate.insert (logicGroup);
503- } else {
504- for (uint32_t lane = 0 ; lane < laneCount; lane++) {
505- chunkStateSimulatorIds[range.baseIndex + lane] = wireSimIds[lane];
506- }
507- }
497+ const PortStateRange& range = portStateIter->second ;
498+ if (!range.isValid ()) continue ;
499+
500+ std::vector<simulator_id_t >& chunkStateSimulatorIds = vulkanLogicAllocation.value ()->getStateSimulatorIds ();
501+ if (std::holds_alternative<std::vector<simulator_id_t >>(simIds)) {
502+ const std::vector<simulator_id_t >& wireSimIds = std::get<std::vector<simulator_id_t >>(simIds);
503+ uint32_t laneCount = wireSimIds.size ();
504+ if (laneCount != range.laneCount ) {
505+ logicGroupsToUpdate.insert (logicGroup);
508506 } else {
509- if (1 != range.laneCount ) {
510- logicGroupsToUpdate.insert (logicGroup);
511- } else {
512- chunkStateSimulatorIds[range.baseIndex ] = std::get<simulator_id_t >(simIds);
507+ for (uint32_t lane = 0 ; lane < laneCount; lane++) {
508+ chunkStateSimulatorIds[range.baseIndex + lane] = wireSimIds[lane];
513509 }
514510 }
511+ } else {
512+ if (1 != range.laneCount ) {
513+ logicGroupsToUpdate.insert (logicGroup);
514+ } else {
515+ chunkStateSimulatorIds[range.baseIndex ] = std::get<simulator_id_t >(simIds);
516+ }
515517 }
516518 }
517519 }
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