[Xtensa] Rename XtensaMCAsmBackend and internalize it

Follow the majority of targets by naming this XXXAsmBackend instead of
XXXMCAsmBackend. Switch to the modern license header text.

Author: MaskRay

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp

@@ -1,6 +1,4 @@
-//===-- XtensaMCAsmBackend.cpp - Xtensa assembler backend -----------------===//
-//
-//                     The LLVM Compiler Infrastructure
+//===----------------------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -24,12 +22,14 @@ using namespace llvm;
 
 namespace llvm {
 class MCObjectTargetWriter;
-class XtensaMCAsmBackend : public MCAsmBackend {
+}
+namespace {
+class XtensaAsmBackend : public MCAsmBackend {
   uint8_t OSABI;
   bool IsLittleEndian;
 
 public:
-  XtensaMCAsmBackend(uint8_t osABI, bool isLE)
+  XtensaAsmBackend(uint8_t osABI, bool isLE)
       : MCAsmBackend(llvm::endianness::little), OSABI(osABI),
         IsLittleEndian(isLE) {}
 
@@ -49,9 +49,9 @@ class XtensaMCAsmBackend : public MCAsmBackend {
     return createXtensaObjectWriter(OSABI, IsLittleEndian);
   }
 };
-} // namespace llvm
+} // namespace
 
-MCFixupKindInfo XtensaMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
+MCFixupKindInfo XtensaAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[Xtensa::NumTargetFixupKinds] = {
       // name                     offset bits  flags
       {"fixup_xtensa_branch_6", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
@@ -144,11 +144,11 @@ static unsigned getSize(unsigned Kind) {
   }
 }
 
-void XtensaMCAsmBackend::applyFixup(const MCAssembler &Asm,
-                                    const MCFixup &Fixup, const MCValue &Target,
-                                    MutableArrayRef<char> Data, uint64_t Value,
-                                    bool IsResolved,
-                                    const MCSubtargetInfo *STI) const {
+void XtensaAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+                                  const MCValue &Target,
+                                  MutableArrayRef<char> Data, uint64_t Value,
+                                  bool IsResolved,
+                                  const MCSubtargetInfo *STI) const {
   MCContext &Ctx = Asm.getContext();
   MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
 
@@ -168,16 +168,16 @@ void XtensaMCAsmBackend::applyFixup(const MCAssembler &Asm,
   }
 }
 
-bool XtensaMCAsmBackend::mayNeedRelaxation(const MCInst &Inst,
-                                           const MCSubtargetInfo &STI) const {
+bool XtensaAsmBackend::mayNeedRelaxation(const MCInst &Inst,
+                                         const MCSubtargetInfo &STI) const {
   return false;
 }
 
-void XtensaMCAsmBackend::relaxInstruction(MCInst &Inst,
-                                          const MCSubtargetInfo &STI) const {}
+void XtensaAsmBackend::relaxInstruction(MCInst &Inst,
+                                        const MCSubtargetInfo &STI) const {}
 
-bool XtensaMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
-                                      const MCSubtargetInfo *STI) const {
+bool XtensaAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
+                                    const MCSubtargetInfo *STI) const {
   uint64_t NumNops24b = Count / 3;
 
   for (uint64_t i = 0; i != NumNops24b; ++i) {
@@ -210,11 +210,11 @@ bool XtensaMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
   return true;
 }
 
-MCAsmBackend *llvm::createXtensaMCAsmBackend(const Target &T,
-                                             const MCSubtargetInfo &STI,
-                                             const MCRegisterInfo &MRI,
-                                             const MCTargetOptions &Options) {
+MCAsmBackend *llvm::createXtensaAsmBackend(const Target &T,
+                                           const MCSubtargetInfo &STI,
+                                           const MCRegisterInfo &MRI,
+                                           const MCTargetOptions &Options) {
   uint8_t OSABI =
       MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
-  return new llvm::XtensaMCAsmBackend(OSABI, true);
+  return new XtensaAsmBackend(OSABI, true);
 }

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp

@@ -163,7 +163,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() {
 
   // Register the MCAsmBackend.
   TargetRegistry::RegisterMCAsmBackend(getTheXtensaTarget(),
-                                       createXtensaMCAsmBackend);
+                                       createXtensaAsmBackend);
 
   // Register the asm target streamer.
   TargetRegistry::RegisterAsmTargetStreamer(getTheXtensaTarget(),

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h

@@ -40,10 +40,10 @@ extern Target TheXtensaTarget;
 MCCodeEmitter *createXtensaMCCodeEmitter(const MCInstrInfo &MCII,
                                          MCContext &Ctx);
 
-MCAsmBackend *createXtensaMCAsmBackend(const Target &T,
-                                       const MCSubtargetInfo &STI,
-                                       const MCRegisterInfo &MRI,
-                                       const MCTargetOptions &Options);
+MCAsmBackend *createXtensaAsmBackend(const Target &T,
+                                     const MCSubtargetInfo &STI,
+                                     const MCRegisterInfo &MRI,
+                                     const MCTargetOptions &Options);
 std::unique_ptr<MCObjectTargetWriter>
 createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian);