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riscv_sim
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executable file
·1542 lines (1542 loc) · 60.1 KB
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)" "(v12_0-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/ivl/system.vpi";
:vpi_module "/usr/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/ivl/va_math.vpi";
:vpi_module "/usr/lib/ivl/v2009.vpi";
S_0x555dbab90170 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x555dbab6d680 .scope module, "RiscV_SingleCycle_tb" "RiscV_SingleCycle_tb" 3 3;
.timescale -9 -12;
v0x555dbabc9610_0 .var "clk", 0 0;
v0x555dbabc96d0_0 .var/i "cycle_count", 31 0;
v0x555dbabc97b0_0 .var/i "error_count", 31 0;
v0x555dbabc9870_0 .var "program_finished", 0 0;
v0x555dbabc9930_0 .var "reset", 0 0;
S_0x555dbab6d240 .scope begin, "$ivl_for_loop0" "$ivl_for_loop0" 3 122, 3 122 0, S_0x555dbab6d680;
.timescale -9 -12;
v0x555dbab90f00_0 .var/2s "i", 31 0;
E_0x555dbab449d0 .event posedge, v0x555dbabc4a70_0;
S_0x555dbabbc050 .scope task, "check_data_memory" "check_data_memory" 3 71, 3 71 0, S_0x555dbab6d680;
.timescale -9 -12;
v0x555dbab94860_0 .var "addr", 31 0;
v0x555dbab9a1e0_0 .var "expected", 31 0;
TD_RiscV_SingleCycle_tb.check_data_memory ;
%fork t_1, S_0x555dbabbc250;
%jmp t_0;
.scope S_0x555dbabbc250;
t_1 ;
%load/vec4 v0x555dbab94860_0;
%addi 3, 0, 32;
%ix/vec4 4;
%load/vec4a v0x555dbabc0eb0, 4;
%load/vec4 v0x555dbab94860_0;
%addi 2, 0, 32;
%ix/vec4 4;
%load/vec4a v0x555dbabc0eb0, 4;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbab94860_0;
%addi 1, 0, 32;
%ix/vec4 4;
%load/vec4a v0x555dbabc0eb0, 4;
%concat/vec4; draw_concat_vec4
%ix/getv 4, v0x555dbab94860_0;
%load/vec4a v0x555dbabc0eb0, 4;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x555dbab813e0_0, 0, 32;
%load/vec4 v0x555dbab813e0_0;
%load/vec4 v0x555dbab9a1e0_0;
%cmp/ne;
%jmp/0xz T_0.0, 6;
%vpi_call/w 3 83 "$error", "\342\235\214 DataMemory[0x%08h] = 0x%08h, expected 0x%08h", v0x555dbab94860_0, v0x555dbab813e0_0, v0x555dbab9a1e0_0 {0 0 0};
%load/vec4 v0x555dbabc97b0_0;
%addi 1, 0, 32;
%store/vec4 v0x555dbabc97b0_0, 0, 32;
%jmp T_0.1;
T_0.0 ;
%vpi_call/w 3 87 "$display", "\342\234\205 DataMemory[0x%08h] = 0x%08h", v0x555dbab94860_0, v0x555dbab9a1e0_0 {0 0 0};
T_0.1 ;
%end;
.scope S_0x555dbabbc050;
t_0 %join;
%end;
S_0x555dbabbc250 .scope begin, "$unm_blk_5" "$unm_blk_5" 3 74, 3 74 0, S_0x555dbabbc050;
.timescale -9 -12;
v0x555dbab813e0_0 .var "read_value", 31 0;
S_0x555dbabbc530 .scope task, "check_register" "check_register" 3 56, 3 56 0, S_0x555dbab6d680;
.timescale -9 -12;
v0x555dbabbc710_0 .var "expected", 31 0;
v0x555dbabbc7f0_0 .var/str "name";
v0x555dbabbc8b0_0 .var/2s "reg_num", 31 0;
TD_RiscV_SingleCycle_tb.check_register ;
%ix/getv/s 4, v0x555dbabbc8b0_0;
%load/vec4a v0x555dbabc73d0, 4;
%load/vec4 v0x555dbabbc710_0;
%cmp/ne;
%jmp/0xz T_1.2, 6;
%vpi_call/w 3 62 "$error", "\342\235\214 %s (x%0d) = 0x%08h, expected 0x%08h", v0x555dbabbc7f0_0, v0x555dbabbc8b0_0, &A<v0x555dbabc73d0, v0x555dbabbc8b0_0 >, v0x555dbabbc710_0 {0 0 0};
%load/vec4 v0x555dbabc97b0_0;
%addi 1, 0, 32;
%store/vec4 v0x555dbabc97b0_0, 0, 32;
%jmp T_1.3;
T_1.2 ;
%vpi_call/w 3 66 "$display", "\342\234\205 %s (x%0d) = 0x%08h", v0x555dbabbc7f0_0, v0x555dbabbc8b0_0, v0x555dbabbc710_0 {0 0 0};
T_1.3 ;
%end;
S_0x555dbabbc970 .scope module, "dut" "RiscV_SingleCycle" 3 13, 4 1 0, S_0x555dbab6d680;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "reset";
P_0x555dbab8fbc0 .param/l "IMEM_SIZE" 0 4 2, +C4<00000000000000000000000000010000>;
P_0x555dbab8fc00 .param/str "PROGRAM_FILE" 0 4 3, "test_programs/program.hex";
v0x555dbabc7760_0 .net "ALUASrc", 0 0, v0x555dbabbec20_0; 1 drivers
v0x555dbabc7820_0 .net "ALUBSrc", 0 0, v0x555dbabbed00_0; 1 drivers
v0x555dbabc7930_0 .net "ALUOp", 3 0, v0x555dbabbedc0_0; 1 drivers
v0x555dbabc7a20_0 .net "ALURes", 31 0, v0x555dbabbd500_0; 1 drivers
v0x555dbabc7ac0_0 .net "ALU_A", 31 0, v0x555dbabc2c30_0; 1 drivers
v0x555dbabc7bd0_0 .net "ALU_B", 31 0, v0x555dbabc3380_0; 1 drivers
v0x555dbabc7ce0_0 .net "BrOp", 4 0, v0x555dbabbee90_0; 1 drivers
v0x555dbabc7df0_0 .net "DMCtrl", 2 0, v0x555dbabbef60_0; 1 drivers
v0x555dbabc7f00_0 .net "DMWr", 0 0, v0x555dbabbf070_0; 1 drivers
v0x555dbabc8030_0 .net "DataRd", 31 0, v0x555dbabc0070_0; 1 drivers
v0x555dbabc8140_0 .net "Funct3", 2 0, L_0x555dbabc9cc0; 1 drivers
v0x555dbabc8200_0 .net "Funct7", 6 0, L_0x555dbabc9fd0; 1 drivers
v0x555dbabc82a0_0 .net "ImmExt", 31 0, v0x555dbabc26b0_0; 1 drivers
v0x555dbabc8390_0 .net "ImmSrc", 2 0, v0x555dbabbf2f0_0; 1 drivers
v0x555dbabc84a0_0 .net "InmediateBits", 24 0, L_0x555dbabca100; 1 drivers
v0x555dbabc8560_0 .net "Instruction", 31 0, L_0x555dbabda830; 1 drivers
v0x555dbabc8600_0 .net "NextPC", 31 0, v0x555dbabc3ae0_0; 1 drivers
v0x555dbabc86f0_0 .net "NextPCsrc", 0 0, v0x555dbabbda40_0; 1 drivers
v0x555dbabc87e0_0 .net "OpCode", 6 0, L_0x555dbabc9a70; 1 drivers
v0x555dbabc88a0_0 .net "PC", 31 0, v0x555dbabc4c40_0; 1 drivers
v0x555dbabc8940_0 .net "PC_plus_4", 31 0, L_0x555dbabda310; 1 drivers
v0x555dbabc8a50_0 .net "RUDataWrSrc", 1 0, v0x555dbabbf4b0_0; 1 drivers
v0x555dbabc8b60_0 .net "RUWr", 0 0, v0x555dbabbf590_0; 1 drivers
v0x555dbabc8c50_0 .net "RU_DataWr", 31 0, v0x555dbabc4440_0; 1 drivers
L_0x7fc1c7a9c018 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>;
v0x555dbabc8d60_0 .net/2u *"_ivl_14", 31 0, L_0x7fc1c7a9c018; 1 drivers
v0x555dbabc8e40_0 .net "clk", 0 0, v0x555dbabc9610_0; 1 drivers
v0x555dbabc8f30_0 .net "rd", 4 0, L_0x555dbabc9bd0; 1 drivers
v0x555dbabc8ff0_0 .net "reset", 0 0, v0x555dbabc9930_0; 1 drivers
v0x555dbabc9090_0 .net "rs1", 4 0, L_0x555dbabc9e40; 1 drivers
v0x555dbabc9130_0 .net "rs2", 4 0, L_0x555dbabc9ee0; 1 drivers
v0x555dbabc91d0_0 .net "ru_rs1", 31 0, L_0x555dbabdb4a0; 1 drivers
v0x555dbabc9270_0 .net "ru_rs2", 31 0, L_0x555dbabdc290; 1 drivers
L_0x555dbabc9a70 .part L_0x555dbabda830, 0, 7;
L_0x555dbabc9bd0 .part L_0x555dbabda830, 7, 5;
L_0x555dbabc9cc0 .part L_0x555dbabda830, 12, 3;
L_0x555dbabc9e40 .part L_0x555dbabda830, 15, 5;
L_0x555dbabc9ee0 .part L_0x555dbabda830, 20, 5;
L_0x555dbabc9fd0 .part L_0x555dbabda830, 25, 7;
L_0x555dbabca100 .part L_0x555dbabda830, 7, 25;
L_0x555dbabda310 .arith/sum 32, v0x555dbabc4c40_0, L_0x7fc1c7a9c018;
S_0x555dbabbcc10 .scope module, "alu_inst" "ALU" 4 141, 5 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 32 "A";
.port_info 1 /INPUT 32 "B";
.port_info 2 /INPUT 4 "ALUOp";
.port_info 3 /OUTPUT 32 "ALURes";
P_0x555dbab660c0 .param/l "ALU_ADD" 1 5 11, C4<0000>;
P_0x555dbab66100 .param/l "ALU_AND" 1 5 20, C4<0111>;
P_0x555dbab66140 .param/l "ALU_OR" 1 5 19, C4<0110>;
P_0x555dbab66180 .param/l "ALU_PASS_B" 1 5 21, C4<1001>;
P_0x555dbab661c0 .param/l "ALU_SLL" 1 5 13, C4<0001>;
P_0x555dbab66200 .param/l "ALU_SLT" 1 5 14, C4<0010>;
P_0x555dbab66240 .param/l "ALU_SLTU" 1 5 15, C4<0011>;
P_0x555dbab66280 .param/l "ALU_SRA" 1 5 18, C4<1101>;
P_0x555dbab662c0 .param/l "ALU_SRL" 1 5 17, C4<0101>;
P_0x555dbab66300 .param/l "ALU_SUB" 1 5 12, C4<1000>;
P_0x555dbab66340 .param/l "ALU_XOR" 1 5 16, C4<0100>;
v0x555dbabbd320_0 .net/s "A", 31 0, v0x555dbabc2c30_0; alias, 1 drivers
v0x555dbabbd420_0 .net "ALUOp", 3 0, v0x555dbabbedc0_0; alias, 1 drivers
v0x555dbabbd500_0 .var/s "ALURes", 31 0;
v0x555dbabbd5c0_0 .net/s "B", 31 0, v0x555dbabc3380_0; alias, 1 drivers
E_0x555dbab457f0 .event anyedge, v0x555dbabbd420_0, v0x555dbabbd320_0, v0x555dbabbd5c0_0;
S_0x555dbabbd720 .scope module, "branch_inst" "BranchUnit" 4 149, 6 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 32 "ru_rs1";
.port_info 1 /INPUT 32 "ru_rs2";
.port_info 2 /INPUT 5 "BrOp";
.port_info 3 /OUTPUT 1 "NextPCsrc";
v0x555dbabbd940_0 .net "BrOp", 4 0, v0x555dbabbee90_0; alias, 1 drivers
v0x555dbabbda40_0 .var "NextPCsrc", 0 0;
v0x555dbabbdb00_0 .net "ru_rs1", 31 0, L_0x555dbabdb4a0; alias, 1 drivers
v0x555dbabbdbf0_0 .net "ru_rs2", 31 0, L_0x555dbabdc290; alias, 1 drivers
E_0x555dbab44e80 .event anyedge, v0x555dbabbd940_0, v0x555dbabbdb00_0, v0x555dbabbdbf0_0;
S_0x555dbabbdd80 .scope module, "control_inst" "ControlUnit" 4 90, 7 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 7 "OpCode";
.port_info 1 /INPUT 3 "Funct3";
.port_info 2 /INPUT 7 "Funct7";
.port_info 3 /OUTPUT 1 "RUWr";
.port_info 4 /OUTPUT 1 "ALUASrc";
.port_info 5 /OUTPUT 1 "ALUBSrc";
.port_info 6 /OUTPUT 4 "ALUOp";
.port_info 7 /OUTPUT 3 "ImmSrc";
.port_info 8 /OUTPUT 5 "BrOp";
.port_info 9 /OUTPUT 1 "DMWr";
.port_info 10 /OUTPUT 3 "DMCtrl";
.port_info 11 /OUTPUT 2 "RUDataWrSrc";
P_0x555dbabbdf60 .param/l "ALU_ADD" 1 7 37, C4<0000>;
P_0x555dbabbdfa0 .param/l "ALU_PASS_B" 1 7 41, C4<1001>;
P_0x555dbabbdfe0 .param/l "ALU_SRA" 1 7 40, C4<1101>;
P_0x555dbabbe020 .param/l "ALU_SRL" 1 7 39, C4<0101>;
P_0x555dbabbe060 .param/l "ALU_SUB" 1 7 38, C4<1000>;
P_0x555dbabbe0a0 .param/l "AUIPC_OPCODE" 1 7 26, C4<0010111>;
P_0x555dbabbe0e0 .param/l "B_TYPE_OPCODE" 1 7 22, C4<1100011>;
P_0x555dbabbe120 .param/l "FUNCT3_ADD_SUB" 1 7 29, C4<000>;
P_0x555dbabbe160 .param/l "FUNCT3_SRL_SRA" 1 7 30, C4<101>;
P_0x555dbabbe1a0 .param/l "FUNCT7_ALT" 1 7 34, C4<0100000>;
P_0x555dbabbe1e0 .param/l "FUNCT7_NORMAL" 1 7 33, C4<0000000>;
P_0x555dbabbe220 .param/l "I_TYPE_OPCODE" 1 7 19, C4<0010011>;
P_0x555dbabbe260 .param/l "JALR_OPCODE" 1 7 21, C4<1100111>;
P_0x555dbabbe2a0 .param/l "JAL_OPCODE" 1 7 24, C4<1101111>;
P_0x555dbabbe2e0 .param/l "LUI_OPCODE" 1 7 25, C4<0110111>;
P_0x555dbabbe320 .param/l "L_TYPE_OPCODE" 1 7 20, C4<0000011>;
P_0x555dbabbe360 .param/l "R_TYPE_OPCODE" 1 7 18, C4<0110011>;
P_0x555dbabbe3a0 .param/l "S_TYPE_OPCODE" 1 7 23, C4<0100011>;
v0x555dbabbec20_0 .var "ALUASrc", 0 0;
v0x555dbabbed00_0 .var "ALUBSrc", 0 0;
v0x555dbabbedc0_0 .var "ALUOp", 3 0;
v0x555dbabbee90_0 .var "BrOp", 4 0;
v0x555dbabbef60_0 .var "DMCtrl", 2 0;
v0x555dbabbf070_0 .var "DMWr", 0 0;
v0x555dbabbf130_0 .net "Funct3", 2 0, L_0x555dbabc9cc0; alias, 1 drivers
v0x555dbabbf210_0 .net "Funct7", 6 0, L_0x555dbabc9fd0; alias, 1 drivers
v0x555dbabbf2f0_0 .var "ImmSrc", 2 0;
v0x555dbabbf3d0_0 .net "OpCode", 6 0, L_0x555dbabc9a70; alias, 1 drivers
v0x555dbabbf4b0_0 .var "RUDataWrSrc", 1 0;
v0x555dbabbf590_0 .var "RUWr", 0 0;
E_0x555dbaaf2c20 .event anyedge, v0x555dbabbf3d0_0, v0x555dbabbf130_0, v0x555dbabbf210_0;
S_0x555dbabbf7d0 .scope module, "dmem_inst" "DataMemory" 4 157, 8 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 32 "Address";
.port_info 1 /INPUT 32 "DataWr";
.port_info 2 /INPUT 1 "DMWr";
.port_info 3 /INPUT 3 "DMCtrl";
.port_info 4 /OUTPUT 32 "DataRd";
P_0x555dbab248c0 .param/l "LB" 1 8 11, C4<000>;
P_0x555dbab24900 .param/l "LB_U" 1 8 14, C4<100>;
P_0x555dbab24940 .param/l "LH" 1 8 12, C4<001>;
P_0x555dbab24980 .param/l "LH_U" 1 8 15, C4<101>;
P_0x555dbab249c0 .param/l "LW" 1 8 13, C4<010>;
P_0x555dbab24a00 .param/l "SB" 1 8 16, C4<000>;
P_0x555dbab24a40 .param/l "SH" 1 8 17, C4<001>;
P_0x555dbab24a80 .param/l "SW" 1 8 18, C4<010>;
L_0x555dbabdc4c0 .functor BUFZ 8, L_0x555dbabdc420, C4<00000000>, C4<00000000>, C4<00000000>;
L_0x555dbabdc7d0 .functor BUFZ 8, L_0x555dbabdc580, C4<00000000>, C4<00000000>, C4<00000000>;
L_0x555dbabdca70 .functor BUFZ 8, L_0x555dbabdc930, C4<00000000>, C4<00000000>, C4<00000000>;
L_0x555dbabdcd10 .functor BUFZ 8, L_0x555dbabdcbd0, C4<00000000>, C4<00000000>, C4<00000000>;
v0x555dbabbfd90_0 .net "Address", 31 0, v0x555dbabbd500_0; alias, 1 drivers
v0x555dbabbfea0_0 .net "DMCtrl", 2 0, v0x555dbabbef60_0; alias, 1 drivers
v0x555dbabbff70_0 .net "DMWr", 0 0, v0x555dbabbf070_0; alias, 1 drivers
v0x555dbabc0070_0 .var "DataRd", 31 0;
v0x555dbabc0110_0 .net "DataWr", 31 0, L_0x555dbabdc290; alias, 1 drivers
v0x555dbabc0200_0 .net *"_ivl_0", 7 0, L_0x555dbabdc420; 1 drivers
v0x555dbabc02c0_0 .net *"_ivl_12", 7 0, L_0x555dbabdc930; 1 drivers
L_0x7fc1c7a9c4e0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
v0x555dbabc03a0_0 .net/2u *"_ivl_14", 31 0, L_0x7fc1c7a9c4e0; 1 drivers
v0x555dbabc0480_0 .net *"_ivl_16", 31 0, L_0x555dbabdc9d0; 1 drivers
v0x555dbabc05f0_0 .net *"_ivl_20", 7 0, L_0x555dbabdcbd0; 1 drivers
L_0x7fc1c7a9c528 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
v0x555dbabc06d0_0 .net/2u *"_ivl_22", 31 0, L_0x7fc1c7a9c528; 1 drivers
v0x555dbabc07b0_0 .net *"_ivl_24", 31 0, L_0x555dbabdcc70; 1 drivers
v0x555dbabc0890_0 .net *"_ivl_4", 7 0, L_0x555dbabdc580; 1 drivers
L_0x7fc1c7a9c498 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
v0x555dbabc0970_0 .net/2u *"_ivl_6", 31 0, L_0x7fc1c7a9c498; 1 drivers
v0x555dbabc0a50_0 .net *"_ivl_8", 31 0, L_0x555dbabdc730; 1 drivers
v0x555dbabc0b30_0 .net "byte0", 7 0, L_0x555dbabdc4c0; 1 drivers
v0x555dbabc0c10_0 .net "byte1", 7 0, L_0x555dbabdc7d0; 1 drivers
v0x555dbabc0cf0_0 .net "byte2", 7 0, L_0x555dbabdca70; 1 drivers
v0x555dbabc0dd0_0 .net "byte3", 7 0, L_0x555dbabdcd10; 1 drivers
v0x555dbabc0eb0 .array "dm", 8192 0, 7 0;
E_0x555dbaba16a0 .event posedge, v0x555dbabbf070_0;
E_0x555dbabbfd20/0 .event anyedge, v0x555dbabbef60_0, v0x555dbabc0b30_0, v0x555dbabc0c10_0, v0x555dbabc0dd0_0;
E_0x555dbabbfd20/1 .event anyedge, v0x555dbabc0cf0_0;
E_0x555dbabbfd20 .event/or E_0x555dbabbfd20/0, E_0x555dbabbfd20/1;
L_0x555dbabdc420 .array/port v0x555dbabc0eb0, v0x555dbabbd500_0;
L_0x555dbabdc580 .array/port v0x555dbabc0eb0, L_0x555dbabdc730;
L_0x555dbabdc730 .arith/sum 32, v0x555dbabbd500_0, L_0x7fc1c7a9c498;
L_0x555dbabdc930 .array/port v0x555dbabc0eb0, L_0x555dbabdc9d0;
L_0x555dbabdc9d0 .arith/sum 32, v0x555dbabbd500_0, L_0x7fc1c7a9c4e0;
L_0x555dbabdcbd0 .array/port v0x555dbabc0eb0, L_0x555dbabdcc70;
L_0x555dbabdcc70 .arith/sum 32, v0x555dbabbd500_0, L_0x7fc1c7a9c528;
S_0x555dbabc1040 .scope module, "imem_inst" "InstructionMemory" 4 84, 9 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 32 "address";
.port_info 1 /OUTPUT 32 "instruction";
P_0x555dbabc1220 .param/l "ADDR_WIDTH" 1 9 9, +C4<00000000000000000000000000000100>;
P_0x555dbabc1260 .param/l "MEM_SIZE" 0 9 2, +C4<00000000000000000000000000010000>;
P_0x555dbabc12a0 .param/str "PROGRAM_FILE" 0 9 3, "test_programs/program.hex";
v0x555dbabc17a0_0 .net *"_ivl_1", 29 0, L_0x555dbabda470; 1 drivers
v0x555dbabc18a0_0 .net *"_ivl_10", 31 0, L_0x555dbabda790; 1 drivers
L_0x7fc1c7a9c0f0 .functor BUFT 1, C4<00000000000000000000000000010011>, C4<0>, C4<0>, C4<0>;
v0x555dbabc1980_0 .net/2u *"_ivl_12", 31 0, L_0x7fc1c7a9c0f0; 1 drivers
L_0x7fc1c7a9c060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x555dbabc1a40_0 .net *"_ivl_5", 1 0, L_0x7fc1c7a9c060; 1 drivers
L_0x7fc1c7a9c0a8 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc1b20_0 .net/2u *"_ivl_6", 31 0, L_0x7fc1c7a9c0a8; 1 drivers
v0x555dbabc1c50_0 .net "address", 31 0, v0x555dbabc4c40_0; alias, 1 drivers
v0x555dbabc1d30_0 .net "address_valid", 0 0, L_0x555dbabda650; 1 drivers
v0x555dbabc1df0_0 .net "aligned_addr", 31 0, L_0x555dbabda510; 1 drivers
v0x555dbabc1ed0_0 .net "instruction", 31 0, L_0x555dbabda830; alias, 1 drivers
v0x555dbabc1fb0 .array "mem", 15 0, 31 0;
L_0x555dbabda470 .part v0x555dbabc4c40_0, 2, 30;
L_0x555dbabda510 .concat [ 30 2 0 0], L_0x555dbabda470, L_0x7fc1c7a9c060;
L_0x555dbabda650 .cmp/gt 32, L_0x7fc1c7a9c0a8, L_0x555dbabda510;
L_0x555dbabda790 .array/port v0x555dbabc1fb0, L_0x555dbabda510;
L_0x555dbabda830 .functor MUXZ 32, L_0x7fc1c7a9c0f0, L_0x555dbabda790, L_0x555dbabda650, C4<>;
S_0x555dbabc14a0 .scope begin, "$ivl_for_loop1" "$ivl_for_loop1" 9 13, 9 13 0, S_0x555dbabc1040;
.timescale -9 -12;
v0x555dbabc16a0_0 .var/2s "i", 31 0;
S_0x555dbabc20d0 .scope module, "immgen_inst" "ImmGen" 4 118, 10 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 25 "InmediateBits";
.port_info 1 /INPUT 3 "ImmSrc";
.port_info 2 /OUTPUT 32 "ImmExt";
P_0x555dbabc2260 .param/l "B_TYPE" 1 10 8, C4<101>;
P_0x555dbabc22a0 .param/l "I_TYPE" 1 10 6, C4<000>;
P_0x555dbabc22e0 .param/l "J_TYPE" 1 10 10, C4<110>;
P_0x555dbabc2320 .param/l "S_TYPE" 1 10 7, C4<001>;
P_0x555dbabc2360 .param/l "U_TYPE" 1 10 9, C4<010>;
v0x555dbabc26b0_0 .var "ImmExt", 31 0;
v0x555dbabc27b0_0 .net "ImmSrc", 2 0, v0x555dbabbf2f0_0; alias, 1 drivers
v0x555dbabc2870_0 .net "InmediateBits", 24 0, L_0x555dbabca100; alias, 1 drivers
E_0x555dbabc2630 .event anyedge, v0x555dbabbf2f0_0, v0x555dbabc2870_0;
S_0x555dbabc29c0 .scope module, "mux_alua_inst" "ALUA" 4 125, 11 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 1 "ALUAsrc";
.port_info 1 /INPUT 32 "PC";
.port_info 2 /INPUT 32 "ru_rs1";
.port_info 3 /OUTPUT 32 "A";
v0x555dbabc2c30_0 .var "A", 31 0;
v0x555dbabc2d40_0 .net "ALUAsrc", 0 0, v0x555dbabbec20_0; alias, 1 drivers
v0x555dbabc2e10_0 .net "PC", 31 0, v0x555dbabc4c40_0; alias, 1 drivers
v0x555dbabc2f10_0 .net "ru_rs1", 31 0, L_0x555dbabdb4a0; alias, 1 drivers
E_0x555dbabc2bd0 .event anyedge, v0x555dbabbec20_0, v0x555dbabc1c50_0, v0x555dbabbdb00_0;
S_0x555dbabc3030 .scope module, "mux_alub_inst" "ALUB" 4 133, 12 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 1 "ALUBsrc";
.port_info 1 /INPUT 32 "ru_rs2";
.port_info 2 /INPUT 32 "ImmExt";
.port_info 3 /OUTPUT 32 "B";
v0x555dbabc3290_0 .net "ALUBsrc", 0 0, v0x555dbabbed00_0; alias, 1 drivers
v0x555dbabc3380_0 .var "B", 31 0;
v0x555dbabc3450_0 .net "ImmExt", 31 0, v0x555dbabc26b0_0; alias, 1 drivers
v0x555dbabc3550_0 .net "ru_rs2", 31 0, L_0x555dbabdc290; alias, 1 drivers
E_0x555dbabc3210 .event anyedge, v0x555dbabbed00_0, v0x555dbabc26b0_0, v0x555dbabbdbf0_0;
S_0x555dbabc36a0 .scope module, "mux_nextpc_inst" "NextPC" 4 175, 13 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 1 "NextPCsrc";
.port_info 1 /INPUT 32 "PC_with_offset";
.port_info 2 /INPUT 32 "ALURes";
.port_info 3 /OUTPUT 32 "NextPC";
v0x555dbabc3a00_0 .net "ALURes", 31 0, v0x555dbabbd500_0; alias, 1 drivers
v0x555dbabc3ae0_0 .var "NextPC", 31 0;
v0x555dbabc3bc0_0 .net "NextPCsrc", 0 0, v0x555dbabbda40_0; alias, 1 drivers
v0x555dbabc3c90_0 .net "PC_with_offset", 31 0, L_0x555dbabda310; alias, 1 drivers
E_0x555dbabc3980 .event anyedge, v0x555dbabbda40_0, v0x555dbabbd500_0, v0x555dbabc3c90_0;
S_0x555dbabc3de0 .scope module, "mux_ru_data_inst" "RUDataWr" 4 166, 14 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 2 "RUDataWrSrc";
.port_info 1 /INPUT 32 "PC_with_offset";
.port_info 2 /INPUT 32 "DataRd";
.port_info 3 /INPUT 32 "ALURes";
.port_info 4 /OUTPUT 32 "DataWr";
P_0x555dbabc3fc0 .param/l "ALURES" 1 14 11, C4<00>;
P_0x555dbabc4000 .param/l "DATARD" 1 14 10, C4<01>;
P_0x555dbabc4040 .param/l "PC_WITH_OFFSET" 1 14 9, C4<10>;
v0x555dbabc4270_0 .net "ALURes", 31 0, v0x555dbabbd500_0; alias, 1 drivers
v0x555dbabc4350_0 .net "DataRd", 31 0, v0x555dbabc0070_0; alias, 1 drivers
v0x555dbabc4440_0 .var "DataWr", 31 0;
v0x555dbabc4510_0 .net "PC_with_offset", 31 0, L_0x555dbabda310; alias, 1 drivers
v0x555dbabc4600_0 .net "RUDataWrSrc", 1 0, v0x555dbabbf4b0_0; alias, 1 drivers
E_0x555dbabc4200 .event anyedge, v0x555dbabbf4b0_0, v0x555dbabc3c90_0, v0x555dbabc0070_0, v0x555dbabbd500_0;
S_0x555dbabc47a0 .scope module, "pc_inst" "ProgramCounter" 4 73, 15 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "reset";
.port_info 2 /INPUT 32 "next_pc";
.port_info 3 /OUTPUT 32 "pc";
v0x555dbabc4a70_0 .net "clk", 0 0, v0x555dbabc9610_0; alias, 1 drivers
v0x555dbabc4b50_0 .net "next_pc", 31 0, v0x555dbabc3ae0_0; alias, 1 drivers
v0x555dbabc4c40_0 .var "pc", 31 0;
v0x555dbabc4d60_0 .net "reset", 0 0, v0x555dbabc9930_0; alias, 1 drivers
E_0x555dbabc49f0 .event posedge, v0x555dbabc4d60_0, v0x555dbabc4a70_0;
S_0x555dbabc4e80 .scope module, "reg_unit_inst" "RegistersUnit" 4 106, 16 1 0, S_0x555dbabbc970;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 5 "rs1";
.port_info 2 /INPUT 5 "rs2";
.port_info 3 /INPUT 5 "rd";
.port_info 4 /INPUT 32 "DataWR";
.port_info 5 /INPUT 1 "RUWr";
.port_info 6 /OUTPUT 32 "ru_rs1";
.port_info 7 /OUTPUT 32 "ru_rs2";
L_0x555dbabda3b0 .functor AND 1, v0x555dbabbf590_0, L_0x555dbabdadc0, C4<1>, C4<1>;
L_0x555dbabdb0c0 .functor AND 1, L_0x555dbabda3b0, L_0x555dbabdaf00, C4<1>, C4<1>;
L_0x555dbabdbb50 .functor AND 1, v0x555dbabbf590_0, L_0x555dbabdba10, C4<1>, C4<1>;
L_0x555dbabdb950 .functor AND 1, L_0x555dbabdbb50, L_0x555dbabdbc50, C4<1>, C4<1>;
v0x555dbabc5180_0 .net "DataWR", 31 0, v0x555dbabc4440_0; alias, 1 drivers
v0x555dbabc5260_0 .net "RUWr", 0 0, v0x555dbabbf590_0; alias, 1 drivers
v0x555dbabc5330_0 .net *"_ivl_0", 31 0, L_0x555dbabda9c0; 1 drivers
v0x555dbabc5400_0 .net *"_ivl_10", 31 0, L_0x555dbabdac40; 1 drivers
L_0x7fc1c7a9c210 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc54c0_0 .net *"_ivl_13", 26 0, L_0x7fc1c7a9c210; 1 drivers
L_0x7fc1c7a9c258 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc55f0_0 .net/2u *"_ivl_14", 31 0, L_0x7fc1c7a9c258; 1 drivers
v0x555dbabc56d0_0 .net *"_ivl_16", 0 0, L_0x555dbabdadc0; 1 drivers
v0x555dbabc5790_0 .net *"_ivl_19", 0 0, L_0x555dbabda3b0; 1 drivers
v0x555dbabc5850_0 .net *"_ivl_20", 0 0, L_0x555dbabdaf00; 1 drivers
v0x555dbabc59a0_0 .net *"_ivl_23", 0 0, L_0x555dbabdb0c0; 1 drivers
v0x555dbabc5a60_0 .net *"_ivl_24", 31 0, L_0x555dbabdb130; 1 drivers
v0x555dbabc5b40_0 .net *"_ivl_26", 6 0, L_0x555dbabdb1d0; 1 drivers
L_0x7fc1c7a9c2a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x555dbabc5c20_0 .net *"_ivl_29", 1 0, L_0x7fc1c7a9c2a0; 1 drivers
L_0x7fc1c7a9c138 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc5d00_0 .net *"_ivl_3", 26 0, L_0x7fc1c7a9c138; 1 drivers
v0x555dbabc5de0_0 .net *"_ivl_30", 31 0, L_0x555dbabdb310; 1 drivers
v0x555dbabc5ec0_0 .net *"_ivl_34", 31 0, L_0x555dbabdb670; 1 drivers
L_0x7fc1c7a9c2e8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc5fa0_0 .net *"_ivl_37", 26 0, L_0x7fc1c7a9c2e8; 1 drivers
L_0x7fc1c7a9c330 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc6080_0 .net/2u *"_ivl_38", 31 0, L_0x7fc1c7a9c330; 1 drivers
L_0x7fc1c7a9c180 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc6160_0 .net/2u *"_ivl_4", 31 0, L_0x7fc1c7a9c180; 1 drivers
v0x555dbabc6240_0 .net *"_ivl_40", 0 0, L_0x555dbabdb770; 1 drivers
L_0x7fc1c7a9c378 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc6300_0 .net/2u *"_ivl_42", 31 0, L_0x7fc1c7a9c378; 1 drivers
v0x555dbabc63e0_0 .net *"_ivl_44", 31 0, L_0x555dbabdb8b0; 1 drivers
L_0x7fc1c7a9c3c0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc64c0_0 .net *"_ivl_47", 26 0, L_0x7fc1c7a9c3c0; 1 drivers
L_0x7fc1c7a9c408 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc65a0_0 .net/2u *"_ivl_48", 31 0, L_0x7fc1c7a9c408; 1 drivers
v0x555dbabc6680_0 .net *"_ivl_50", 0 0, L_0x555dbabdba10; 1 drivers
v0x555dbabc6740_0 .net *"_ivl_53", 0 0, L_0x555dbabdbb50; 1 drivers
v0x555dbabc6800_0 .net *"_ivl_54", 0 0, L_0x555dbabdbc50; 1 drivers
v0x555dbabc68c0_0 .net *"_ivl_57", 0 0, L_0x555dbabdb950; 1 drivers
v0x555dbabc6980_0 .net *"_ivl_58", 31 0, L_0x555dbabdbe50; 1 drivers
v0x555dbabc6a60_0 .net *"_ivl_6", 0 0, L_0x555dbabdab00; 1 drivers
v0x555dbabc6b20_0 .net *"_ivl_60", 6 0, L_0x555dbabdbef0; 1 drivers
L_0x7fc1c7a9c450 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x555dbabc6c00_0 .net *"_ivl_63", 1 0, L_0x7fc1c7a9c450; 1 drivers
v0x555dbabc6ce0_0 .net *"_ivl_64", 31 0, L_0x555dbabdc0c0; 1 drivers
L_0x7fc1c7a9c1c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x555dbabc6fd0_0 .net/2u *"_ivl_8", 31 0, L_0x7fc1c7a9c1c8; 1 drivers
v0x555dbabc70b0_0 .net "clk", 0 0, v0x555dbabc9610_0; alias, 1 drivers
v0x555dbabc7150_0 .net "rd", 4 0, L_0x555dbabc9bd0; alias, 1 drivers
v0x555dbabc7210_0 .net "rs1", 4 0, L_0x555dbabc9e40; alias, 1 drivers
v0x555dbabc72f0_0 .net "rs2", 4 0, L_0x555dbabc9ee0; alias, 1 drivers
v0x555dbabc73d0 .array "ru", 0 31, 31 0;
v0x555dbabc7490_0 .net "ru_rs1", 31 0, L_0x555dbabdb4a0; alias, 1 drivers
v0x555dbabc7550_0 .net "ru_rs2", 31 0, L_0x555dbabdc290; alias, 1 drivers
L_0x555dbabda9c0 .concat [ 5 27 0 0], L_0x555dbabc9e40, L_0x7fc1c7a9c138;
L_0x555dbabdab00 .cmp/eq 32, L_0x555dbabda9c0, L_0x7fc1c7a9c180;
L_0x555dbabdac40 .concat [ 5 27 0 0], L_0x555dbabc9bd0, L_0x7fc1c7a9c210;
L_0x555dbabdadc0 .cmp/ne 32, L_0x555dbabdac40, L_0x7fc1c7a9c258;
L_0x555dbabdaf00 .cmp/eq 5, L_0x555dbabc9bd0, L_0x555dbabc9e40;
L_0x555dbabdb130 .array/port v0x555dbabc73d0, L_0x555dbabdb1d0;
L_0x555dbabdb1d0 .concat [ 5 2 0 0], L_0x555dbabc9e40, L_0x7fc1c7a9c2a0;
L_0x555dbabdb310 .functor MUXZ 32, L_0x555dbabdb130, v0x555dbabc4440_0, L_0x555dbabdb0c0, C4<>;
L_0x555dbabdb4a0 .functor MUXZ 32, L_0x555dbabdb310, L_0x7fc1c7a9c1c8, L_0x555dbabdab00, C4<>;
L_0x555dbabdb670 .concat [ 5 27 0 0], L_0x555dbabc9ee0, L_0x7fc1c7a9c2e8;
L_0x555dbabdb770 .cmp/eq 32, L_0x555dbabdb670, L_0x7fc1c7a9c330;
L_0x555dbabdb8b0 .concat [ 5 27 0 0], L_0x555dbabc9bd0, L_0x7fc1c7a9c3c0;
L_0x555dbabdba10 .cmp/ne 32, L_0x555dbabdb8b0, L_0x7fc1c7a9c408;
L_0x555dbabdbc50 .cmp/eq 5, L_0x555dbabc9bd0, L_0x555dbabc9ee0;
L_0x555dbabdbe50 .array/port v0x555dbabc73d0, L_0x555dbabdbef0;
L_0x555dbabdbef0 .concat [ 5 2 0 0], L_0x555dbabc9ee0, L_0x7fc1c7a9c450;
L_0x555dbabdc0c0 .functor MUXZ 32, L_0x555dbabdbe50, v0x555dbabc4440_0, L_0x555dbabdb950, C4<>;
L_0x555dbabdc290 .functor MUXZ 32, L_0x555dbabdc0c0, L_0x7fc1c7a9c378, L_0x555dbabdb770, C4<>;
S_0x555dbabc9370 .scope task, "print_state" "print_state" 3 28, 3 28 0, S_0x555dbab6d680;
.timescale -9 -12;
v0x555dbabc9550_0 .var/str "label";
TD_RiscV_SingleCycle_tb.print_state ;
%vpi_call/w 3 31 "$display", "\012========== %s ==========", v0x555dbabc9550_0 {0 0 0};
%vpi_call/w 3 32 "$display", "Cycle: %0d | Time: %0t", v0x555dbabc96d0_0, $time {0 0 0};
%vpi_call/w 3 33 "$display", "PC = 0x%08h", v0x555dbabc88a0_0 {0 0 0};
%vpi_call/w 3 34 "$display", "Instr = 0x%08h", v0x555dbabc8560_0 {0 0 0};
%vpi_call/w 3 35 "$display", "OpCode = 0b%07b", v0x555dbabc87e0_0 {0 0 0};
%vpi_call/w 3 36 "$display", "ALURes = 0x%08h (%0d)", v0x555dbabc7a20_0, v0x555dbabc7a20_0 {0 0 0};
%vpi_call/w 3 37 "$display", "NextPC = 0x%08h", v0x555dbabc8600_0 {0 0 0};
%vpi_call/w 3 38 "$display", "\012Registers:" {0 0 0};
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x555dbabc73d0, 4;
%vpi_call/w 3 39 "$display", " x1 = 0x%08h (%0d)", &A<v0x555dbabc73d0, 1>, S<0,vec4,s32> {1 0 0};
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x555dbabc73d0, 4;
%vpi_call/w 3 40 "$display", " x2 = 0x%08h (%0d)", &A<v0x555dbabc73d0, 2>, S<0,vec4,s32> {1 0 0};
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x555dbabc73d0, 4;
%vpi_call/w 3 41 "$display", " x3 = 0x%08h (%0d)", &A<v0x555dbabc73d0, 3>, S<0,vec4,s32> {1 0 0};
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x555dbabc73d0, 4;
%vpi_call/w 3 42 "$display", " x4 = 0x%08h (%0d)", &A<v0x555dbabc73d0, 4>, S<0,vec4,s32> {1 0 0};
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x555dbabc73d0, 4;
%vpi_call/w 3 43 "$display", " x5 = 0x%08h (%0d)", &A<v0x555dbabc73d0, 5>, S<0,vec4,s32> {1 0 0};
%vpi_call/w 3 44 "$display", "\012Control Signals:" {0 0 0};
%vpi_call/w 3 45 "$display", " RUWr = %b", v0x555dbabc8b60_0 {0 0 0};
%vpi_call/w 3 46 "$display", " ALUASrc = %b", v0x555dbabc7760_0 {0 0 0};
%vpi_call/w 3 47 "$display", " ALUBSrc = %b", v0x555dbabc7820_0 {0 0 0};
%vpi_call/w 3 48 "$display", " ALUOp = 0b%04b", v0x555dbabc7930_0 {0 0 0};
%vpi_call/w 3 49 "$display", " BrOp = 0b%05b", v0x555dbabc7ce0_0 {0 0 0};
%vpi_call/w 3 50 "$display", " NextPCsrc = %b", v0x555dbabc86f0_0 {0 0 0};
%vpi_call/w 3 51 "$display", " DMWr = %b", v0x555dbabc7f00_0 {0 0 0};
%end;
.scope S_0x555dbabc47a0;
T_3 ;
%wait E_0x555dbabc49f0;
%load/vec4 v0x555dbabc4d60_0;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x555dbabc4c40_0, 0;
%jmp T_3.1;
T_3.0 ;
%load/vec4 v0x555dbabc4b50_0;
%assign/vec4 v0x555dbabc4c40_0, 0;
T_3.1 ;
%jmp T_3;
.thread T_3;
.scope S_0x555dbabc1040;
T_4 ;
%fork t_3, S_0x555dbabc14a0;
%jmp t_2;
.scope S_0x555dbabc14a0;
t_3 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x555dbabc16a0_0, 0, 32;
T_4.0 ;
%load/vec4 v0x555dbabc16a0_0;
%cmpi/s 16, 0, 32;
%jmp/0xz T_4.1, 5;
%pushi/vec4 19, 0, 32;
%ix/getv/s 4, v0x555dbabc16a0_0;
%store/vec4a v0x555dbabc1fb0, 4, 0;
%load/vec4 v0x555dbabc16a0_0;
%addi 1, 0, 32;
%cast2;
%store/vec4 v0x555dbabc16a0_0, 0, 32;
%jmp T_4.0;
T_4.1 ;
%end;
.scope S_0x555dbabc1040;
t_2 %join;
%vpi_call/w 9 19 "$readmemb", P_0x555dbabc12a0, v0x555dbabc1fb0 {0 0 0};
%vpi_call/w 9 22 "$display", "\342\234\205 InstructionMemory initialized:" {0 0 0};
%vpi_call/w 9 23 "$display", " Size: %0d instructions (%0d bytes)", P_0x555dbabc1260, 32'sb00000000000000000000000001000000 {0 0 0};
%vpi_call/w 9 24 "$display", " Address width: %0d bits", P_0x555dbabc1220 {0 0 0};
%vpi_call/w 9 25 "$display", " Max address: 0x%08h", 32'sb00000000000000000000000000111100 {0 0 0};
%end;
.thread T_4;
.scope S_0x555dbabbdd80;
T_5 ;
%wait E_0x555dbaaf2c20;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x555dbabbec20_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x555dbabbedc0_0, 0, 4;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555dbabbf2f0_0, 0, 3;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x555dbabbee90_0, 0, 5;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x555dbabbf070_0, 0, 1;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555dbabbef60_0, 0, 3;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x555dbabbf4b0_0, 0, 2;
%load/vec4 v0x555dbabbf3d0_0;
%dup/vec4;
%pushi/vec4 51, 0, 7;
%cmp/u;
%jmp/1 T_5.0, 6;
%dup/vec4;
%pushi/vec4 19, 0, 7;
%cmp/u;
%jmp/1 T_5.1, 6;
%dup/vec4;
%pushi/vec4 3, 0, 7;
%cmp/u;
%jmp/1 T_5.2, 6;
%dup/vec4;
%pushi/vec4 103, 0, 7;
%cmp/u;
%jmp/1 T_5.3, 6;
%dup/vec4;
%pushi/vec4 99, 0, 7;
%cmp/u;
%jmp/1 T_5.4, 6;
%dup/vec4;
%pushi/vec4 35, 0, 7;
%cmp/u;
%jmp/1 T_5.5, 6;
%dup/vec4;
%pushi/vec4 111, 0, 7;
%cmp/u;
%jmp/1 T_5.6, 6;
%dup/vec4;
%pushi/vec4 55, 0, 7;
%cmp/u;
%jmp/1 T_5.7, 6;
%dup/vec4;
%pushi/vec4 23, 0, 7;
%cmp/u;
%jmp/1 T_5.8, 6;
%jmp T_5.9;
T_5.0 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%load/vec4 v0x555dbabbf130_0;
%cmpi/e 0, 0, 3;
%flag_mov 8, 4;
%jmp/0 T_5.10, 8;
%load/vec4 v0x555dbabbf210_0;
%cmpi/e 0, 0, 7;
%flag_mov 9, 4;
%jmp/0 T_5.12, 9;
%pushi/vec4 0, 0, 4;
%jmp/1 T_5.13, 9;
T_5.12 ; End of true expr.
%pushi/vec4 8, 0, 4;
%jmp/0 T_5.13, 9;
; End of false expr.
%blend;
T_5.13;
%jmp/1 T_5.11, 8;
T_5.10 ; End of true expr.
%load/vec4 v0x555dbabbf130_0;
%cmpi/e 5, 0, 3;
%flag_mov 9, 4;
%jmp/0 T_5.14, 9;
%load/vec4 v0x555dbabbf210_0;
%cmpi/e 0, 0, 7;
%flag_mov 10, 4;
%jmp/0 T_5.16, 10;
%pushi/vec4 5, 0, 4;
%jmp/1 T_5.17, 10;
T_5.16 ; End of true expr.
%pushi/vec4 13, 0, 4;
%jmp/0 T_5.17, 10;
; End of false expr.
%blend;
T_5.17;
%jmp/1 T_5.15, 9;
T_5.14 ; End of true expr.
%pushi/vec4 0, 0, 1;
%load/vec4 v0x555dbabbf130_0;
%concat/vec4; draw_concat_vec4
%jmp/0 T_5.15, 9;
; End of false expr.
%blend;
T_5.15;
%jmp/0 T_5.11, 8;
; End of false expr.
%blend;
T_5.11;
%store/vec4 v0x555dbabbedc0_0, 0, 4;
%jmp T_5.9;
T_5.1 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%load/vec4 v0x555dbabbf130_0;
%cmpi/e 5, 0, 3;
%flag_get/vec4 4;
%jmp/0 T_5.20, 4;
%load/vec4 v0x555dbabbf210_0;
%pushi/vec4 32, 0, 7;
%cmp/e;
%flag_get/vec4 4;
%and;
T_5.20;
%flag_set/vec4 8;
%jmp/0 T_5.18, 8;
%pushi/vec4 13, 0, 4;
%jmp/1 T_5.19, 8;
T_5.18 ; End of true expr.
%pushi/vec4 0, 0, 1;
%load/vec4 v0x555dbabbf130_0;
%concat/vec4; draw_concat_vec4
%jmp/0 T_5.19, 8;
; End of false expr.
%blend;
T_5.19;
%store/vec4 v0x555dbabbedc0_0, 0, 4;
%jmp T_5.9;
T_5.2 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 1, 0, 2;
%store/vec4 v0x555dbabbf4b0_0, 0, 2;
%load/vec4 v0x555dbabbf130_0;
%store/vec4 v0x555dbabbef60_0, 0, 3;
%jmp T_5.9;
T_5.3 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 16, 0, 5;
%store/vec4 v0x555dbabbee90_0, 0, 5;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x555dbabbf4b0_0, 0, 2;
%jmp T_5.9;
T_5.4 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbec20_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555dbabbf2f0_0, 0, 3;
%pushi/vec4 1, 0, 2;
%load/vec4 v0x555dbabbf130_0;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x555dbabbee90_0, 0, 5;
%jmp T_5.9;
T_5.5 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf070_0, 0, 1;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x555dbabbf2f0_0, 0, 3;
%load/vec4 v0x555dbabbf130_0;
%store/vec4 v0x555dbabbef60_0, 0, 3;
%jmp T_5.9;
T_5.6 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbec20_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 16, 0, 5;
%store/vec4 v0x555dbabbee90_0, 0, 5;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x555dbabbf4b0_0, 0, 2;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x555dbabbf2f0_0, 0, 3;
%jmp T_5.9;
T_5.7 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x555dbabbedc0_0, 0, 4;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x555dbabbf2f0_0, 0, 3;
%jmp T_5.9;
T_5.8 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbf590_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbec20_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x555dbabbed00_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x555dbabbf2f0_0, 0, 3;
%jmp T_5.9;
T_5.9 ;
%pop/vec4 1;
%jmp T_5;
.thread T_5, $push;
.scope S_0x555dbabc4e80;
T_6 ;
%wait E_0x555dbab449d0;
%load/vec4 v0x555dbabc5260_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_6.2, 9;
%load/vec4 v0x555dbabc7150_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/ne;
%flag_get/vec4 4;
%and;
T_6.2;
%flag_set/vec4 8;
%jmp/0xz T_6.0, 8;
%load/vec4 v0x555dbabc5180_0;
%load/vec4 v0x555dbabc7150_0;
%pad/u 7;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x555dbabc73d0, 0, 4;
T_6.0 ;
%jmp T_6;
.thread T_6;
.scope S_0x555dbabc20d0;
T_7 ;
%wait E_0x555dbabc2630;
%load/vec4 v0x555dbabc27b0_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_7.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_7.1, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_7.2, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_7.3, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_7.4, 6;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x555dbabc26b0_0, 0, 32;
%jmp T_7.6;
T_7.0 ;
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 24, 6;
%replicate 20;
%load/vec4 v0x555dbabc2870_0;
%parti/s 12, 13, 5;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x555dbabc26b0_0, 0, 32;
%jmp T_7.6;
T_7.1 ;
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 24, 6;
%replicate 20;
%load/vec4 v0x555dbabc2870_0;
%parti/s 7, 18, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 5, 0, 2;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x555dbabc26b0_0, 0, 32;
%jmp T_7.6;
T_7.2 ;
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 24, 6;
%replicate 19;
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 24, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 0, 2;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 6, 18, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 4, 1, 2;
%concat/vec4; draw_concat_vec4
%concati/vec4 0, 0, 1;
%store/vec4 v0x555dbabc26b0_0, 0, 32;
%jmp T_7.6;
T_7.3 ;
%load/vec4 v0x555dbabc2870_0;
%parti/s 20, 5, 4;
%concati/vec4 0, 0, 12;
%store/vec4 v0x555dbabc26b0_0, 0, 32;
%jmp T_7.6;
T_7.4 ;
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 24, 6;
%replicate 11;
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 24, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 8, 5, 4;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 1, 13, 5;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x555dbabc2870_0;
%parti/s 10, 14, 5;
%concat/vec4; draw_concat_vec4
%concati/vec4 0, 0, 1;
%store/vec4 v0x555dbabc26b0_0, 0, 32;
%jmp T_7.6;
T_7.6 ;
%pop/vec4 1;
%jmp T_7;
.thread T_7, $push;
.scope S_0x555dbabc29c0;
T_8 ;
%wait E_0x555dbabc2bd0;
%load/vec4 v0x555dbabc2d40_0;
%flag_set/vec4 8;
%jmp/0 T_8.0, 8;
%load/vec4 v0x555dbabc2e10_0;
%jmp/1 T_8.1, 8;
T_8.0 ; End of true expr.
%load/vec4 v0x555dbabc2f10_0;
%jmp/0 T_8.1, 8;
; End of false expr.
%blend;
T_8.1;
%store/vec4 v0x555dbabc2c30_0, 0, 32;
%jmp T_8;
.thread T_8, $push;
.scope S_0x555dbabc3030;
T_9 ;
%wait E_0x555dbabc3210;
%load/vec4 v0x555dbabc3290_0;
%flag_set/vec4 8;
%jmp/0 T_9.0, 8;
%load/vec4 v0x555dbabc3450_0;
%jmp/1 T_9.1, 8;
T_9.0 ; End of true expr.
%load/vec4 v0x555dbabc3550_0;
%jmp/0 T_9.1, 8;
; End of false expr.
%blend;
T_9.1;
%store/vec4 v0x555dbabc3380_0, 0, 32;
%jmp T_9;
.thread T_9, $push;
.scope S_0x555dbabbcc10;
T_10 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x555dbabbd500_0, 0, 32;
%end;
.thread T_10, $init;
.scope S_0x555dbabbcc10;
T_11 ;
%wait E_0x555dbab457f0;
%load/vec4 v0x555dbabbd420_0;
%dup/vec4;
%pushi/vec4 0, 0, 4;
%cmp/u;
%jmp/1 T_11.0, 6;
%dup/vec4;
%pushi/vec4 8, 0, 4;
%cmp/u;
%jmp/1 T_11.1, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_11.2, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_11.3, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_11.4, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_11.5, 6;
%dup/vec4;
%pushi/vec4 5, 0, 4;
%cmp/u;
%jmp/1 T_11.6, 6;
%dup/vec4;
%pushi/vec4 13, 0, 4;
%cmp/u;
%jmp/1 T_11.7, 6;
%dup/vec4;
%pushi/vec4 6, 0, 4;
%cmp/u;
%jmp/1 T_11.8, 6;
%dup/vec4;
%pushi/vec4 7, 0, 4;
%cmp/u;
%jmp/1 T_11.9, 6;
%dup/vec4;
%pushi/vec4 9, 0, 4;
%cmp/u;
%jmp/1 T_11.10, 6;
%jmp T_11.11;
T_11.0 ;
%load/vec4 v0x555dbabbd320_0;
%load/vec4 v0x555dbabbd5c0_0;
%add;
%store/vec4 v0x555dbabbd500_0, 0, 32;
%jmp T_11.11;
T_11.1 ;
%load/vec4 v0x555dbabbd320_0;
%load/vec4 v0x555dbabbd5c0_0;
%sub;
%store/vec4 v0x555dbabbd500_0, 0, 32;
%jmp T_11.11;
T_11.2 ;
%load/vec4 v0x555dbabbd320_0;
%load/vec4 v0x555dbabbd5c0_0;
%ix/vec4 4;
%shiftl 4;
%store/vec4 v0x555dbabbd500_0, 0, 32;
%jmp T_11.11;
T_11.3 ;
%load/vec4 v0x555dbabbd320_0;
%load/vec4 v0x555dbabbd5c0_0;
%cmp/s;
%flag_get/vec4 5;
%pad/u 32;
%store/vec4 v0x555dbabbd500_0, 0, 32;
%jmp T_11.11;
T_11.4 ;
%load/vec4 v0x555dbabbd320_0;