- MVP
- Better variable support
- Support for 64-bit ELF
- Support for 32-bit (protected) and 16-bit (real) modes; cr, dr, eflags and segments (cs, fs, etc.)
- Support for: SSE, SSE2, SSE3, SSSE3, SSE4_1, SSE4_2, MMX x86(-64) extensions
- Support for AVX and AVX2 extensions
- moving into beta phase (release of beta0)...
- Support for most of "normal" (to norm-part6) x86-64 instructions
- Transforming
Memenum into struct - Parser support for closures
()other than memory address - Support for "modifiers" that is:
base:mod1:mod2 - Support for comptime mathematical evaluations (
$()closure) - Support for constant user defined mathematical values (that aren't symbols, but inline immediates)
- Improved segmentation (allow prefixing with
%and free up#prefix) - Support for includes
- Support for label attributes (
#()closure) - Migration (from legacy
*gen_ins) to new codegen API (GenAPIstruct) - Fix OSOP and ASOP prefixes (Operand/Address Size Override Prefix (for memory))
- Optimize
Instructionstruct
- Variables overhaul (labels as variables)
- Switch
!prefix for keywords for. - Relocation/Symbol overhaul (use of
@()closure) - Tests for relocations and other things
- Better target handling (ELF rewritten from zero)
- Support for custom sections (with
.sectionkeyword)
- Create documentation (including better readme ;))
- Overall polish:
- Allow for
typein labels attributes. - Make sections also symbols.
- Allow for use of
PREFIX_VALinExtSymbolRef. - Move some of logic in
src/main.rsto separate file. - Mem support for (R)IP (addresing like
($10)) - Allow for different size relocations (
relXXandabsXX) - Fix
in,lea,wrf/gsbase,loopXXandoutinstructions. - Add missing
lgdtandlidtinstructions. - Allow using
lock,repXXmnemonics as prefix - Allow for using symbols/relocations in more than one place (as address or value under address;
.deref/.refdirectives) - Remove
.assemble()frommatchstatement insrc/core/comp.rs:compile_instructionand move insidecompile_label - Create
.debug_assemble()(--debug) - Limit lifetimes, where they are unnecessary (use owned values)
- Replace
Strings withArc<str>/Rc<str>. - Allow for usage of multi threads to compile labels/sections
- Revamp
ATypeandsrc/pre/chk.rsin favor ofCheckAPI(like is withGenAPI) - Revamp errors (better readability) with explainations
- Create
src/docs/errors.mdand--explain=[ECD]
- Allow for
- moving into beta-avx phase...
Goal: implement most of AVX based (E)VEX instructions
- Prepare
pasm's syntax for AVX-512 - Prepare backend for AVX-512 (add
IS_BCSTflag to Mem, add support for masks, etc. in parser) - implement EVEX support
- ISA implementation (divided in 15 parts):
- avx-ext-0
- avx-ext-1
- avx-ext-2
- avx-ext-3
- avx-ext-4
- avx-ext-5
- avx-ext-6
- avx-ext-7
- avx-ext-8
- avx-ext-9
- avx-ext-a
- avx-ext-b
- avx-ext-c
- avx-ext-d
- avx-ext-e (vsib)
- Move to beta-intel-apx
Goal: implement support for Intel APX
- cleanup
Instructioninsrc/shr/ast.rs(it is barely readable) and prepare it for Intel APX - Patch
{sae}and{er}modifiers inCheckAPI(actually check if it's correct). - implement support for APX in syntax
- implement checking for APX (in
pre::chkn::CheckAPI) - partial migration toCheckAPI:D - implement EEVEX (extended EVEX; all 3 variants without ones for ctestcc and ccmpcc) and REX2 prefixes support
- ISA implementantation (divided in 8 parts; legacy instructions included):
- intel-apx-0 (legacy instructions without setcc)
- intel-apx-1 (ctestcc + ccmpcc + EEVEX support for cond. test and cmp)
- intel-apx-2 (cfcmovcc)
- intel-apx-3 (setcc)
- intel-apx-4 (push2/pop2)
- Move to beta-min
Goal: support for smaller x86-64 ISA extensions (around 284 new mnemonics)
- missing x86-64 instructions
- move to rc
Goal: extensive testing, polish and optimizations of assembler, less updates/commits
- Support for 16-bit addressing
- Add
nobitsdirective forsection's - Allow for
protected public function label_name: - Allow for long jumps (
jmp ptrXX:YYandjmp m16:XX) - Move revitalization
- move to stable
- release of
stableversion