uart_writer.sv

`timescale 1ns/1ps

// This file is public domain, it can be freely copied without restrictions.
// SPDX-License-Identifier: CC0-1.0
// Adder DUT


module uart_writer (
  input logic clk,
  input logic reset,
  input logic [31:0] clk_per_tick,
  input logic [7:0] bits,
  input logic start_transmission,
  output logic tx,
  output logic end_transmission,
  output logic error
);
  typedef enum logic [1:0] {idle, start, transmit, stop} states;
  states state;
  logic [3:0] bit_number;
  logic [7:0] internal_data;
  logic [31:0] count_clk;

  always_ff @(posedge reset)
  begin
    state <= idle;
    end_transmission <= 0;
    error <= 0;
    count_clk <= 0;
    bit_number <= 0;
    tx <= 1;
  end

  always_ff @(posedge clk)
  begin
    case (state)

    idle:
    begin
      if(start_transmission) begin
        end_transmission <= 0;
        error <= 0;
        count_clk <= 0;
        tx <= 0;
        state <= start;
        internal_data <= bits;
      end
    end

    start: 
    begin
      if (count_clk < clk_per_tick-1)
      begin
        count_clk <= count_clk + 1;
      end
      else
      begin
        count_clk <= 0;
        state <= transmit;
      end
    end

    transmit:
    begin
      if ((count_clk < clk_per_tick-1) & !(bit_number == 8))
      begin
        tx <= internal_data[bit_number];
        count_clk <= count_clk + 1;
      end
      else
      begin
        count_clk <= 0;
        bit_number <= bit_number + 1;
      end
      if (bit_number == 8)
      begin
        state <= stop;
        bit_number <= 0;
      end

    end

    stop:
    begin
    if (count_clk < clk_per_tick/2)
      begin
        tx <= 1;
        count_clk <= count_clk + 1;
      end
      else
      begin
        count_clk <= 0;
        state <= idle;
        end_transmission <= 1;
      end
    end

    default:
      state <= idle;
    
    endcase
  end
endmodule : uart_writer