diff --git a/turing_complete_interface/circuit_parser.py b/turing_complete_interface/circuit_parser.py
index 301ff0b..e1cebea 100644
--- a/turing_complete_interface/circuit_parser.py
+++ b/turing_complete_interface/circuit_parser.py
@@ -93,6 +93,19 @@ class CircuitWire:
     label: str
     positions: list[tuple[int, int]]
 
+    def __init__(self, id: int, is_bytes_or_kind: bool | str, color, label, positions):
+        if isinstance(is_bytes_or_kind, str):
+            self.kind = is_bytes_or_kind
+        elif is_bytes_or_kind:
+            self.kind = "ck_bytes"
+        else:
+            self.kind = "ck_bit"
+
+        self.id = id
+        self.color = color
+        self.label = label
+        self.positions = positions
+
     @property
     def is_byte(self):
         if self.kind == "ck_qword":
diff --git a/turing_complete_interface/circuit_viewer.py b/turing_complete_interface/circuit_viewer.py
index 01a9118..5a3ea25 100644
--- a/turing_complete_interface/circuit_viewer.py
+++ b/turing_complete_interface/circuit_viewer.py
@@ -443,7 +443,7 @@ def view_circuit(circuit, node, space, output_handler: Callable[[pg.Surface], Wo
     screen = pg.display.set_mode((W, H), FLAGS)
     if output_handler is not None:
         output_handler = output_handler(screen)
-    font = pg.font.Font("turing_complete_interface/Px437_IBM_BIOS.ttf", FONT_SIZE)
+    font = pg.font.Font(f"{Path(__file__).parent.resolve()}/Px437_IBM_BIOS.ttf", FONT_SIZE)
     W, H = screen.get_size()
     view = CircuitView.centered(screen, space=space, scale_x=40, circuit=circuit)
 
diff --git a/turing_complete_interface/from_verilog.py b/turing_complete_interface/from_verilog.py
index 03ebffc..1f9e61b 100644
--- a/turing_complete_interface/from_verilog.py
+++ b/turing_complete_interface/from_verilog.py
@@ -42,5 +42,5 @@
 
         save_folder.mkdir(parents=True, exist_ok=True)
         save = save_folder / "circuit.data"
-        save.write_text(circuit.to_string())
+        save.write_bytes(circuit.to_bytes())
         print("Wrote to", save)
diff --git a/turing_complete_interface/verilog_parser.py b/turing_complete_interface/verilog_parser.py
index 98a7270..f2c49f1 100644
--- a/turing_complete_interface/verilog_parser.py
+++ b/turing_complete_interface/verilog_parser.py
@@ -203,7 +203,7 @@ def named_port(self, port_name: Token, ref):
     def assign_decl(self, target, source):
         target, target_bits = self.visit(target)
         source, source_bits = self.visit(source)
-        self.wires[target][0].append((source_bits, source, target_bits))
+        self.wires[target][0].append((source_bits, (None, source), target_bits))
 
 
 verilog_to_tc = json.load(Path(__file__).with_name("verilog_components.json").open())