From b03c76ec4aa5d8c7fe7fbe6e500e361beabaf1b2 Mon Sep 17 00:00:00 2001 From: Jeferson Chaves Date: Thu, 18 Sep 2025 20:05:18 -0300 Subject: [PATCH 1/2] Fix Verilog-2001 violation: enforce standard-compliant inout handling. Fixing a Verilog-2001 standard violation that breaks simulation, synthesis, and formal verification in standards-compliant tools: Bidirectional ports (inout) must be driven using continuous assignments (assign), which are only valid for nets (e.g., wire). Using inout reg is explicitly disallowed. Tri-state and bidirectional ports must therefore be implemented with continuous assignments on nets. By contrast, reg types are intended for procedural assignments (inside always blocks), which cannot synthesize proper tri-state drivers for I/O pads. --- rtl/sdram.sv | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/rtl/sdram.sv b/rtl/sdram.sv index c4d96e48..b6e95154 100644 --- a/rtl/sdram.sv +++ b/rtl/sdram.sv @@ -23,7 +23,7 @@ module sdram ( // interface to the MT48LC16M16 chip - inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + inout [15:0] SDRAM_DQ, // 16 bit bidirectional data bus output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus output reg SDRAM_DQML, // byte mask output reg SDRAM_DQMH, // byte mask @@ -66,6 +66,8 @@ module sdram output [15:0] ss_out ); +reg SDRAM_DQ_CONTROL; + assign SDRAM_nCS = 0; assign SDRAM_CKE = 1; assign {SDRAM_DQMH,SDRAM_DQML} = SDRAM_A[12:11]; @@ -200,6 +202,8 @@ localparam CMD_LOAD_MODE = 3'b000; wire [1:0] dqm = {we & ~a[0], we & a[0]}; +assign SDRAM_DQ = (SDRAM_DQ_CONTROL)? data: {16{1'bZ}}; + // SDRAM state machines always @(posedge clk) begin reg [15:0] last_data[3]; @@ -207,10 +211,14 @@ always @(posedge clk) begin if(state == STATE_START) SDRAM_BA <= (mode == MODE_NORMAL) ? bank : 2'b00; - SDRAM_DQ <= 'Z; + if({ram_req,we,mode,state} == {2'b11, MODE_NORMAL, STATE_CONT }) + SDRAM_DQ_CONTROL <= 1'b1; + else + SDRAM_DQ_CONTROL <= 1'b0; + casex({ram_req,we,mode,state}) {2'b1X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_ACTIVE; - {2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ} <= {CMD_WRITE, data}; + {2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= {CMD_WRITE}; {2'b10, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_READ; {2'b0X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_AUTO_REFRESH; From 1a39324e4e37d87ebd8b626671d590a8979e6b8c Mon Sep 17 00:00:00 2001 From: Jeferson Chaves Date: Fri, 19 Sep 2025 21:24:02 -0300 Subject: [PATCH 2/2] Improving code for inout handling (fix for verilog 2001 violation) --- rtl/sdram.sv | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/rtl/sdram.sv b/rtl/sdram.sv index b6e95154..db93ec79 100644 --- a/rtl/sdram.sv +++ b/rtl/sdram.sv @@ -210,23 +210,18 @@ always @(posedge clk) begin reg [15:0] data_reg; if(state == STATE_START) SDRAM_BA <= (mode == MODE_NORMAL) ? bank : 2'b00; - - if({ram_req,we,mode,state} == {2'b11, MODE_NORMAL, STATE_CONT }) - SDRAM_DQ_CONTROL <= 1'b1; - else - SDRAM_DQ_CONTROL <= 1'b0; casex({ram_req,we,mode,state}) - {2'b1X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_ACTIVE; - {2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= {CMD_WRITE}; - {2'b10, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_READ; - {2'b0X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_AUTO_REFRESH; + {2'b1X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_ACTIVE, 1'b0}; + {2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_WRITE, 1'b1}; + {2'b10, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_READ, 1'b0}; + {2'b0X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_AUTO_REFRESH, 1'b0}; // init - {2'bXX, MODE_LDM, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_LOAD_MODE; - {2'bXX, MODE_PRE, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_PRECHARGE; + {2'bXX, MODE_LDM, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_LOAD_MODE, 1'b0}; + {2'bXX, MODE_PRE, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_PRECHARGE, 1'b0}; - default: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_NOP; + default: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ_CONTROL} <= {CMD_NOP, 1'b0}; endcase casex({ram_req,mode,state})