Question: ready signal to store Game saves ?

[rp-jt]

Hello,

I have been trying to implement game saves in the JTNGP core, but the thing is that the SD system already implemented in hps_io requires a byte per clock speed for each block written or read in in the .sav image, and we are storing the cartridge's flash memory within SDRAM, in which it is not possible to obtain a byte per clock.

I'm also trying to avoid using a BRAM intermediate, so I thought of adding a sd_buff_wait signal in hps_io, similar to how ioctl_wait can be used to stop the NVRAM download process. However, in Main_MiSTer's user_io.cpp side, it is clear that this process works in a per block manner, making it difficult to change it to write bytes without breaking something else in the way.

Any suggestions on how I could solve this? Thanks!

[birdybro]

The NES core does it without BRAM.

https://github.com/MiSTer-devel/NES_MiSTer/blob/master/NES.sv#L1085-L1120

wire save_busy;
reg save_rd, save_wr;
reg save_wait;
reg [18:0] save_addr;

always @(posedge clk) begin

	if(~save_busy & ~save_rd & ~save_wr) save_wait <= 0;

	if(~bk_busy) begin
		save_addr <= '1;
		save_wait <= 0;
	end
	else if(sd_ack & ~save_busy ) begin
		if(~bk_loading && (save_addr != {sd_lba[9:0], sd_buff_addr})) begin
			save_rd <= 1;
			save_addr <= {sd_lba[9:0], sd_buff_addr};
			save_wait <= 1;
		end
		if(bk_loading && sd_buff_wr) begin
			save_wr <= 1;
			save_addr <= {sd_lba[9:0], sd_buff_addr};
			save_wait <= 1;
		end
	end
	if(~bk_busy | save_busy | bram_en) {save_rd, save_wr} <= 0;
end

reg bk_pending;
wire save_written, mapper_has_flashsaves;
always @(posedge clk) begin
	if ((mapper_flags[25] || fds || mapper_has_flashsaves) && ~OSD_STATUS && save_written)
		bk_pending <= 1'b1;
	else if (bk_state)
		bk_pending <= 1'b0;
end

https://github.com/MiSTer-devel/NES_MiSTer/blob/master/NES.sv#L1020-L1022

wire [24:0] ch2_addr = sleep_savestate ? Savestate_SDRAMAddr :
                       mapper_has_flashsaves ? {6'b000000, save_addr} : // PRG-ROM
                       {7'b0001111, save_addr[17:0]};                   // CARTRAM

This section shows the save/load with wait (stall sd block transfer) logic. This basically makes it so instead of one byte per clock it will operate at the speed of the SDRAM which usually is much much faster than the cpu clock of any core. The NES core only uses BRAM for EEPROM saves, not for battery backed saves or FDS saves, I think.

[rp-jt]

Thank you! I'll give it a try!