[AArch64] Add a AArch64InstrInfo::isFpOrNEON method for checking physical register call. NFC

Author: davemgreen

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -978,11 +978,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
       // For GPRs, we only care to clear out the 64-bit register.
       if (MCRegister XReg = getRegisterOrZero(Reg, HasSVE))
         GPRsToZero.set(XReg);
-    } else if (AArch64::FPR128RegClass.contains(Reg) ||
-               AArch64::FPR64RegClass.contains(Reg) ||
-               AArch64::FPR32RegClass.contains(Reg) ||
-               AArch64::FPR16RegClass.contains(Reg) ||
-               AArch64::FPR8RegClass.contains(Reg)) {
+    } else if (AArch64InstrInfo::isFpOrNEON(Reg)) {
       // For FPRs,
       if (MCRegister XReg = getRegisterOrZero(Reg, HasSVE))
         FPRsToZero.set(XReg);

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -4188,17 +4188,24 @@ bool AArch64InstrInfo::hasBTISemantics(const MachineInstr &MI) {
   }
 }
 
+bool AArch64InstrInfo::isFpOrNEON(Register Reg) {
+  if (Reg == 0)
+    return false;
+  assert(Reg.isPhysical() && "Expected physical register in isFpOrNEON");
+  return AArch64::FPR128RegClass.contains(Reg) ||
+         AArch64::FPR64RegClass.contains(Reg) ||
+         AArch64::FPR32RegClass.contains(Reg) ||
+         AArch64::FPR16RegClass.contains(Reg) ||
+         AArch64::FPR8RegClass.contains(Reg);
+}
+
 bool AArch64InstrInfo::isFpOrNEON(const MachineInstr &MI) {
   auto IsFPR = [&](const MachineOperand &Op) {
     if (!Op.isReg())
       return false;
     auto Reg = Op.getReg();
     if (Reg.isPhysical())
-      return AArch64::FPR128RegClass.contains(Reg) ||
-             AArch64::FPR64RegClass.contains(Reg) ||
-             AArch64::FPR32RegClass.contains(Reg) ||
-             AArch64::FPR16RegClass.contains(Reg) ||
-             AArch64::FPR8RegClass.contains(Reg);
+      return isFpOrNEON(Reg);
 
     const TargetRegisterClass *TRC = ::getRegClass(MI, Reg);
     return TRC == &AArch64::FPR128RegClass ||

llvm/lib/Target/AArch64/AArch64InstrInfo.h

@@ -251,6 +251,9 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
   /// Returns the immediate offset operator of a load/store.
   static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI);
 
+  /// Returns whether the physical register is FP or NEON.
+  static bool isFpOrNEON(Register Reg);
+
   /// Returns whether the instruction is FP or NEON.
   static bool isFpOrNEON(const MachineInstr &MI);
 

llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

@@ -16,6 +16,7 @@
 
 #include "AArch64PBQPRegAlloc.h"
 #include "AArch64.h"
+#include "AArch64InstrInfo.h"
 #include "AArch64RegisterInfo.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -32,14 +33,6 @@ using namespace llvm;
 
 namespace {
 
-#ifndef NDEBUG
-bool isFPReg(unsigned reg) {
-  return AArch64::FPR32RegClass.contains(reg) ||
-         AArch64::FPR64RegClass.contains(reg) ||
-         AArch64::FPR128RegClass.contains(reg);
-}
-#endif
-
 bool isOdd(unsigned reg) {
   switch (reg) {
   default:
@@ -147,8 +140,10 @@ bool isOdd(unsigned reg) {
 }
 
 bool haveSameParity(unsigned reg1, unsigned reg2) {
-  assert(isFPReg(reg1) && "Expecting an FP register for reg1");
-  assert(isFPReg(reg2) && "Expecting an FP register for reg2");
+  assert(AArch64InstrInfo::isFpOrNEON(reg1) &&
+         "Expecting an FP register for reg1");
+  assert(AArch64InstrInfo::isFpOrNEON(reg2) &&
+         "Expecting an FP register for reg2");
 
   return isOdd(reg1) == isOdd(reg2);
 }