Skip to content

Commit 27412d2

Browse files
committed
Fix time
1 parent 06cd477 commit 27412d2

1 file changed

Lines changed: 1 addition & 1 deletion

File tree

cpu/time.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ module tinyQV_time (
4343
/* verilator lint_on PINMISSING */
4444

4545
wire [31:4] reg_buf;
46-
tinyqv_buffer i_regbuf[31:4] ( .X(reg_buf), .A({register[3:0], register[31:8]}) );
46+
tinyqv_buffer i_regbuf[31:4] ( .X(reg_buf), .A({mtimecmp[3:0], mtimecmp[31:8]}) );
4747
always @(posedge clk) mtimecmp[31:4] <= reg_buf;
4848

4949
always @(posedge clk) begin

0 commit comments

Comments
 (0)