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| 1 | +--- |
| 2 | +title: Benefits of using Azure NetApp Files for electronic design automation | Microsoft Docs |
| 3 | +description: Explains the solution Azure NetApp Files provides for meeting the needs of the semiconductor and chip design industry. Presents test scenarios running a standard industry benchmark for electronic design automation (EDA) using Azure NetApp Files. |
| 4 | +services: azure-netapp-files |
| 5 | +documentationcenter: '' |
| 6 | +author: b-juche |
| 7 | +manager: '' |
| 8 | +editor: '' |
| 9 | + |
| 10 | +ms.assetid: |
| 11 | +ms.service: azure-netapp-files |
| 12 | +ms.workload: storage |
| 13 | +ms.tgt_pltfrm: na |
| 14 | +ms.devlang: na |
| 15 | +ms.topic: conceptual |
| 16 | +ms.date: 04/24/2020 |
| 17 | +ms.author: b-juche |
| 18 | +--- |
| 19 | +# Benefits of using Azure NetApp Files for electronic design automation |
| 20 | + |
| 21 | +Time-to-market (TTM) is a critical consideration for the semiconductor and chip design industry. The industry has high bandwidth and low latency needs for storage. This article explains the solution Azure NetApp Files provides for meeting the industry’s needs. It presents test scenarios running a standard industry benchmark for electronic design automation (EDA) using Azure NetApp Files. |
| 22 | + |
| 23 | +## Test scenario configurations |
| 24 | + |
| 25 | +The tests involve three scenarios with the following configurations. |
| 26 | + |
| 27 | +| Scenario | Volumes | Clients<br> SLES15 D16s_v3 | |
| 28 | +|----------------|---------------|--------------------------------| |
| 29 | +| One | 1 | 1 | |
| 30 | +| Two | 6 | 24 | |
| 31 | +| Three | 12 | 24 | |
| 32 | + |
| 33 | +The first scenario addresses how far a single volume can be driven. |
| 34 | + |
| 35 | +The second and the third scenarios evaluate the limits of a single Azure NetApp Files endpoint. They investigate the potential benefits of I/O upper limits and latency. |
| 36 | + |
| 37 | +## Test scenario results |
| 38 | + |
| 39 | +The following table summarizes the test scenarios results. |
| 40 | + |
| 41 | +| Scenario | I/O rate<br> at 2 ms | I/O rate<br> at the edge | Throughput<br> at 2 ms | Throughput<br> at the edge | |
| 42 | +|-------------------|---------------------------|--------------------------------|-----------------------------|----------------------------------| |
| 43 | +| 1 volume | 39,601 | 49,502 | 692 MiB/s | 866 MiB/s | |
| 44 | +| 6 volumes | 255,613 | 317,000 | 4,577 MiB/s | 5,568 MiB/s | |
| 45 | +| 12 volumes | 256,612 | 319,196 | 4,577 MiB/s | 5,709 MiB/s | |
| 46 | + |
| 47 | +The single-volume scenario represents the basic application configuration. It's the baseline scenario for follow-on test scenarios. |
| 48 | + |
| 49 | +The six-volume scenario demonstrates a linear increase (600%) relative to the single-volume workload. All volumes within a single virtual network are accessed over a single IP address. |
| 50 | + |
| 51 | +The 12-volume scenario demonstrates a general decrease in latency over the six-volume scenario. But it doesn’t have a corresponding increase in achievable throughput. |
| 52 | + |
| 53 | +The following graph illustrates the latency and operations rate for the EDA workload on Azure NetApp Files. |
| 54 | + |
| 55 | + |
| 56 | + |
| 57 | +The following graph illustrates the latency and throughput for the EDA workload on Azure NetApp Files. |
| 58 | + |
| 59 | + |
| 60 | + |
| 61 | +## Layout of test scenarios |
| 62 | + |
| 63 | +The table below summarizes the layout of the test scenarios. |
| 64 | + |
| 65 | +| Test scenario | Total number of directories | Total number of files | |
| 66 | +|----------------------|------------------------------------|------------------------------| |
| 67 | +| 1 volume | 88,000 | 880,000 | |
| 68 | +| 6 volumes | 568,000 | 5,680,000 | |
| 69 | +| 12 volumes | 568,000 | 5,680,000 | |
| 70 | + |
| 71 | +The complete workload is a mixture of concurrently running functional and physical phases. It represents a typical flow from one set of EDA tools to another. |
| 72 | + |
| 73 | +The functional phase consists of initial specifications and a logical design. The physical phase takes place when the logical design is converted to a physical chip. During the sign-off and tape-out phases, final checks are completed, and the design is delivered to a foundry for manufacturing. |
| 74 | + |
| 75 | +The functional phases include a mixture of sequential and random read and write I/O. The functional phases are metadata intensive, like file stat and access calls. Although metadata operations are effectively without size, the read and write operations range between less than 1 K and 16 K. Most reads are between 4 K and 16 K. Most writes are 4 K or less. The physical phases are composed of sequential read and write operations entirely, with a mixture of 32 K and 64 K OP sizes. |
| 76 | + |
| 77 | +In the graphs above, most of the throughput comes from the sequential physical phases of workload. The I/O comes from the small random and metadata-intensive functional phases. Both phases happen in parallel. |
| 78 | + |
| 79 | +In conclusion, you can pair Azure compute with Azure NetApp Files for EDA design to get scalable bandwidth. |
| 80 | + |
| 81 | +## Next steps |
| 82 | + |
| 83 | +- [Solution architectures using Azure NetApp Files](azure-netapp-files-solution-architectures.md) |
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