Elaboration results with hierarchy, parameters, and structural complexity metrics

[maria-jomy]

Summary
I'm exploring whether Slang can produce elaboration results that show module hierarchy with parameterization details and structural complexity metrics (or data that could lead to gate count estimates), without requiring full synthesis.

Background
I've been using the yosys-slang plugin to analyze large SystemVerilog designs, but encountered some limitations and performance issues during the elaboration/lowering phase. Before investing more time in debugging the plugin integration, I wanted to understand if Slang itself can provide the type of structural information I need.

What I'm looking for
After parsing and elaborating a SystemVerilog design, I'd like to extract:

Module instance counts - How many instances of each module type exist in the elaborated design
Hierarchical structure - The parent-child relationships between module instances
Parameter values - The resolved parameter values for each instance (e.g., WIDTH, DEPTH, etc.)
Instance paths - Full hierarchical paths for each instance
Structural metrics - Per-module complexity indicators such as:
Number of flip-flops/registers (from always_ff blocks or inferred storage)
Number of combinational logic blocks (from always_comb, assign, etc.)
Port counts and bit widths
Memory instances (arrays, RAMs)

Example desired output:

top_module (52 logic cells, 8 registers)
├── submodule_A #(.WIDTH(32), .DEPTH(8)) (21 cells, 4 DFFs)
│ └── leaf_module #(.WIDTH(32)) (8 cells, 2 DFFs)
├── submodule_A #(.WIDTH(64), .DEPTH(16)) (21 cells, 4 DFFs)
│ └── leaf_module #(.WIDTH(64)) (8 cells, 2 DFFs)
└── submodule_B #(.SIZE(4)) (15 cells, 3 DFFs)

Summary:

• submodule_A: 2 instances, 42 total cells, 8 total DFFs
• submodule_B: 1 instance, 15 cells, 3 DFFs
• leaf_module: 2 instances, 16 total cells, 4 total DFFs

Questions:

1. Does Slang's AST provide enough information to extract this? I know the AST contains the full design structure, but I'm unclear if instance-level parameter resolution and structural complexity data are accessible.

2. Can Slang count structural elements like registers and logic blocks before synthesis? I understand these wouldn't be final gate counts, but even rough estimates based on:
   Sequential blocks (always_ff, declared logic with clock sensitivity)
   Combinational expressions (operators, function calls)
   Memory arrays
   This would be useful for early complexity analysis.

3. Is there a recommended approach/API for traversing elaborated instances? Should I be looking at specific AST node types or visitor patterns?

4.Would --ast-json output contain this information, or would I need to write a custom C++ tool that uses Slang as a library to traverse the elaborated design?

[MikePopoloski]

Yes, all of this information is in the AST, and available via the C++ API or via the JSON output. If you run into specific issues when trying to use it I can assist but beyond that I don't have time to walk you though using the library. If you're very lost I would suggest running your questions through your preferred LLM and letting it help you figure out how to get what you want out of slang.

[maria-jomy]

Hi @MikePopoloski,

Thanks for your helpful response! I appreciate the guidance on the C++ API and JSON options.

Just to confirm my understanding:

1. Slang performs RTL-level elaboration only - resolving parameters, expanding generate blocks, and building the complete design hierarchy - but does NOT perform gate-level synthesis. The elaborated output preserves RTL abstractions rather than converting them to gate primitives.

2 .For gate-level information (gate counts, netlists, gate primitives), I would need to use a separate synthesis tool like Yosys ( with the slang plugin loaded) that consumes slang's elaborated output as input.

3. The AST/JSON output contains:

• Full elaborated design with resolved parameters
• RTL constructs: variables, nets, assignments, operators, behavioral blocks
• But NOT directly gate-level details - gate counts can only be inferred indirectly from RTL structures like always_ff blocks and combinational expressions
  Is this understanding correct? I want to make sure I'm setting realistic expectations for what slang can provide before I start building on top of it.

Thanks again for your help!

[MikePopoloski]

Yes, that's correct.